SU1191910A1 - Device for restoring processor operation - Google Patents

Abstract

A DEVICE FOR RESTORING A CPU PROCESS, containing a fault latch register, firmware control unit, interrupt node, register, switch and the first OR element, and the fault latch register information input is connected to the processor fault output, the first fault latch register reset input and sync input the interrupt node is connected to the first micro-operation microprocessor of the microprogram control unit, the address input of which is connected to the interrupt address output of the interrupt node, the interrupt signal output of which is one with the first. the reset input of the register, the second reset input of which and the second reset input of the register of latching failures are the input of the initial installation of the device, the output of which is connected to the installation input of the register, the output of which is connected to the input of the switch, the output of which is connected to the inputs of the first OR element, characterized in that , in order to increase the reliability of the device by preventing microcircuits from looping when it crashes, a counter, six AND elements and a second OR element are entered into it, and the output of the first OR element is connected with the direct input of the first element And, with the first direct input of the second element And, and with the first direct input of the third element And, the second direct input of the third element And connected to the output of the counter, the third direct and inverse inputs of the third element And connected to the input device mode, the output of the third element I is connected to the blocking input of the microprogram control unit, the second output of micro-operations of which is connected to the direct input of the fourth element (LI and the first direct input of the fifth element I, the second direct and inverse inputs the output of which is connected respectively to the device mode input, the first register reset input and the first input of the second element OR, the second and third inputs and the output of which are connected respectively to the output of the fourth AND element, to the input of the initial setup of the device and to the counter reset input, summing the input and output of which are connected respectively with the output of the sixth element And and with the inverse input of the first element And, the output of which is connected to the first input of interrupt requests of the interrupt node, the second input of the app The interrupt dew of which is connected to the output of the second element I, the input and the third direct inputs of which are connected respectively to the inverse input of the first element I and the input of the device mode, the inverse input

Description

the sixth element (and And is connected to the output of the counter and to the first inverse of the fourth element And, the second inverse of the input of which is connected to the direct input of the sixth element And and with the inverse of the fifth element I. 2. The device according to claim 1, about Likewise, the microprogram control block contains a microinstruction memory node, a microinstruction register, a decoder, a switch, a pulse generator, and a group of elements, the input of the address of the microprogrammed control block connected to the first information input of the switch, the output of which is Connected with the address input 10 of the microinstructions memory node, the output of which is connected to the information input of the register of microinstructions, the output of which is connected to the information input of the decoder, the outputs of the first group of which are the first and second outputs of the microoperations of the block And the inverse of the blocking input , the direct inputs and outputs of the elements AND of a group are connected respectively to the output of the pulse generator and to the control inputs of the switch, the microinstructions register and the decoder, the output of the second group of inputs rows is connected to a second data input switch.

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The invention relates to computing, in particular, to devices that improve the reliability of operation of processors, and can be applied to processors with firmware control.

The purpose of the invention is to increase reliability by preventing the firmware from looping during a crash.

Figure 1 shows the block diagram of the device; FIG. 2 is a block diagram of a firmware control block; FIG. 3 is a block diagram of the interrupt node.

The device for restoring the work of the processors (Fig. 1) contains the register of failures fixing 1, the microprogram control unit, the alarms node 3, the register 4, the switch 5, the counter 6, the elements AND 7-12 the elements OR 13-14, the output 15 of the processor, the input 16 device modes, address input 17 of microprogram control unit 2, interlock input 18 of microprogram control unit 2, outputs 19-20 of micro-operations of microprogram control block 2, bits 21-22 of input 16 of device mode, input 23 of the initial installation of the device.

The microprogram control unit 2 (FIG. 2) contains a micro-command memory node 24, micro-command register 25, a decoder 26, a switch 27, a pulse generator 28, an AND 29 group of elements. The interrupt node (FIG. 3) contains a request register 30, a group of elements OR 31, element AND 32, element OR 33.

Register 1 commit failures is designed to fix failures that occur in blocks and nodes of the processor. Information about failures goes to the register 1 of failures from the output 15 of the failed processor.

Information about the failure, fix-. the bath in register 1 for failures using switch 5 is classified by type B depending on the time of occurrence. The result of the classification is recorded in register 4,

Firmware control unit 2 generates control signals for the entire device. The micro-command memory node 24 contains micro-instructions readable to register 25. The field of micro-commands is decrypted by decipher 26, the address of the next micro-command is selected by switch 27. Forming the control series is synchronous

Signals are carried out by generating 28 pulses. The blocking of the control sync series of sync signals is performed using the AND 29 group of elements.

Interrupt node 3 is designed to force control of the microprograms to handle special cases - failures. In the event of a failure by node 3, a request for a firmware interrupt is generated, which is issued to the firmware control unit 2. In addition to the request, the initial address of the fault handling firmware is transferred to block 2. After the request is satisfied, a signal is generated that resets the source of the request — register 4.

The device for restoring the operation of the processor works as follows.

When the processor is turned on, all its elements are reset. Thus, when the device initial input 23 is energized, the zero state (reset) of the fault fix register 1, the register 4 and the counter 6 is set to zero. The initial installation 23 of the device is excited by pressing the Reset key of the processor machine.

During the operation of the processor, failures occurring in its devices and blocks from the output 15 of the processor fails, go to register 1 of failures. Fixed faults using switch 5 are classified by type depending on the time of their occurrence, as well as repeatable and non-repeatable. The information on the types of failures is recorded in register 4. If at least one bit of register 4 is set up through the OR 13 element, a request for a microprogram interrupt is issued to call the microprogram to handle the arising situation.

So, if counter 6 is not filled, i.e. there is no transfer signal from its most significant bit, then the signal at the output of the counter corresponds to O, element 7 is open and element 10 is closed. Therefore, the first bit of register 30 of the interrupt 3 node request is set. Setting the first bit of register 30 at zero value of the second bit opens element 32, a signal from you 9104

the course of which enters the group of elements OR 31 of node 3 to form the initial address of the repeat firmware. In addition, the signal through the element OR 33 causes a reset of the register 4 and opens the element AND 8, the signal from the output of the open element. This And 8 causes an increase in the content of the counter 6 per unit. The address formed by the group of elements OR 31 and the signal from the output of the element OR 33 arrive at the input 17 of the microprogram control unit 2 to the switch 27. The address of the microcommand issued by node 3 is used to select the microcommand. Transition to firmware repetition is underway.

In the absence of failures during the execution of the firmware repetition program, the corresponding microcommand of this firmware clears the register of fixations of failures 1 by increasing the signal at the first output of microoperation 19 of block 2. The execution of the command continues. The last microinstruction of the executing command excites the signal at the output 20 of the microprogram control unit 2,

which, if the counter 6 is not filled, opens the element AND 9, the signal from whose output through the element OR 14 is fed to the reset input of the counter 6.

If a control mode is set in the program status word, the sign of which enters the device at the input of 16 excitation modes of discharge 21, then resetting the counter 6 takes place

is when the last microcommand of the current command is executed, regardless of its state. Thus, the element And 12 opens, the signal from the output of which through the element OR 14

enters the reset input of the counter 6.

If there is a fault, when executing the repeat firmware, the error signal from output 15 fails

in register 1, commit fails and, as indicated by Bbmie, in register 4.

The set register bit 4 when the counter is empty 6 opens the element And 7, the signal from the output

which establishes the query register 30 of node 3 of the interrupts, and, as described above, a transition is formed to the repeated execution of microprobe

repetition rates. When you go back to the execution of the repeat firmware, register 4 is reset and counter 6 is incremented by the signal through AND 8

In case of multiple failures during the execution of the repeat firmware or during a single command, counter 6 is incremented each time the repeat firmware is entered. When the specified failure threshold is exceeded, a counter is generated using counter 6, which prevents the repeat firmware from being executed again after the next failure.

In this case, with the control mask open, the program status word entering the bit 21 of the mode inputs 16, through the AND 10 element at the interrupt node 3, is a request to execute the control firmware. The request to execute the repeat firmware is denied by the AND 7 element. In this case, the second bit of the register 30 of the node 3 interrupt request is set. The signal of the installed second bit of register 30 pos | Tupaet on a group of elements OR 31 of node 3. To form the initial address of the control firmware. In addition, the signal through the element OR 33 causes a reset of the register 4. An increase in the content of the counter 6 is not performed. The address formed by the group of elements OR 31 and the signal from the output of the element OR 33 are fed to the input 17 of the microprogram control unit 2 to the switch 27. The address of the microcommand issued by node 3 is used to select the microcommand. The transition to the execution of the control firmware is underway. The control firmware provides the formation of an urgent interruption from the control circuits.

In case the signal 6 is inserted by the counter 6, and the control mask in the program status word is closed, then the switch to the repeat and control firmware is not performed. Then, if the failure stop mode is set, the discharge signal 22 of which comes from the mode 16 input, opens the element 11, the output of which is fed to the input 18 of the microprogram control unit 2, where it blocks the output of the sync pulses using the group of elements 29. The exit from this state is accomplished by pressing the reset key of the processor machine as indicated above,

If the failure stop relays are not set, then the synchronization stop is not performed, the failure indication in the 1 register of failures is signaled, and the request for a microprogram interrupt in register 4 is retained, and the calculations continue. The result of the calculations is unpredictable.

Thus, the proposed device improves the reliability of the processor, providing the ability to work with multiple failures, preventing the repeat firmware from looping. In addition, when a given number of failures are exceeded, the transition to the control firmware, which analyzes the situation and ensures the formation of an urgent interruption from the control circuits, will occur.

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Claims (2)

A DEVICE FOR RESTORING A PROCESSOR'S OPERATION, comprising a fault fix register, a microprogram control unit, an interrupt node, a register, a switch, and a first OR element, wherein the information of the fault fix register is connected to the processor failure output, the first input of the fault fix register reset and the sync input of the interrupt node are connected to the first microoperation output of the microprogram control unit, the address input of which is connected to the output of the interrupt address of the interrupt node, the output of the interrupt signal of which is connected to first. register reset input, the second input of the reset of which and the second input of the reset of the register for fixing faults are the input of the initial installation of the device, the output of which is connected to the installation input of the register, the output of which is connected to the input of the switch, the output of which is connected to the inputs of the first OR element, characterized in that, in order to increase the reliability of the device by preventing microprograms from looping during failures, a counter, six AND elements and a second OR element are introduced into it, and the output of the first OR element is connected to a straight line by the input of the first AND element, with the first direct input of the second AND element and with the first direct input of the third AND element, the second direct input of the third AND element is connected to the counter output, the third direct and inverse inputs of the third AND element are connected to the device mode input, the output of the third element And it is connected to the blocking input of the microprogram control unit, the second microoperation output of which is connected to the g direct input of the fourth AND element and to the first direct input of the fifth And element, the second direct and inverse inputs and output of which the second are connected respectively to the device mode input, the first input of the register reset and the first input of the second OR element, the second and third inputs and output of which are connected respectively to the output of the fourth AND element, with the input of the device’s initial setup and with the counter reset input, summing the input and output which are connected respectively to the output of the sixth AND element and the inverse input of the first AND element, whose output is connected to the first input of interrupt requests for the interrupt node, the second input of interrupt requests which connected to the outlet of the second AND gate, and a third straight vtroy inputs of which are respectively connected to an inverted input of the first AND gate and the input of the device mode, the inverting input SU ... 1191910 of the sixth element And is connected to the output of the counter and with the first inverse input of the fourth element And, the second inverse input of which is connected to the direct input of the sixth element And and with the inverse input of the fifth element I. 2. The device according to claim 1, wherein the firmware control unit comprises a micro-memory memory unit, a micro-command register, a decoder, a switch, a pulse generator and a group of AND elements, the input of the address of the firmware control unit being connected to the first information input of the switch the output of which is connected to the address input of the micro-command memory node, the output of which is connected to the information input of the micro-command register, the output of which is connected to the information input of the decoder, the outputs of the first group of which are are the first and second outputs of the unit’s microoperations, the inverse inputs of the group of elements AND are connected to the blocking input of the block, the direct inputs and outputs of the elements and groups are connected respectively to the output of the pulse generator and to the control inputs of the switch, the register of microcommands, and the decoder, the output of the second group of inputs of which connected to the second information input of the switch.