SU1176338A2 - Interface - Google Patents

Abstract

1. DEVICE FOR PAIRING by author. St. No. 754403, which means that, in order to increase the speed of the device, the account register, the comparison node and the counter are entered, the first and second inputs of the counter are connected respectively to the second output of the synchronization unit and the output of the control node, and the output with the first input of the comparison node, the output of the control node connected to the fifth input, the first and second information inputs of the account register are connected respectively to the outputs of the first information register and the driver-receiver node, and the control input and output - respectively a seventh and output control unit. the second input of the comparison node. 2. The device according to claim 1, characterized in that the control node contains a control signal register, a group of inputs and the first input of which are the second and fourth inputs of the node, two groups of elements AND, the outputs of which are connected to the fourth and second outputs of the node, respectively switch, subscriber identification register, termination trigger. and the element And, with the first, second and third outputs of the register of signals. the controls are the first, fifth and sixth outputs of the node respectively, and the fourth, fifth and sixth outputs are respectively connected to the control inputs of the AND elements of the first group, the subscriber identification register and the switch, the first and second outputs of which are connected respectively to the third and seventh node outputs, second input of the register of signals, control and information. By the primary input of the subscriber identification register, the outputs of which are connected to the information inputs of the AND elements of the first group, the first information in the 1sode of the switch is the first. the input of the node, and the second information input is connected to the third input of the node and the first input of the I element, the second input of which and the first inputs of the EL section AND of the second group are connected respectively CO 00 to the seventh output and the group of outputs of the control signal register, the second inputs of the elements And the second group is connected to the output of the end of communication trigger, the first and second inputs of which are connected respectively to the fifth input of the node and the output of the element I.

Description

The invention relates to computing, can be used to interface two electronic computers (COMPUTERS) with various input / output interfaces, for example, an M6000 computer with an EC computer and is complementary to the author. St. 754403. The aim of the invention is to increase the speed of the device when exchanging information. Figure 1 presents the block diagram of the device; Fig. 2 shows functional diagrams of the control node, the readiness signal generation node and the address generation node; FIG. 3 is a functional diagram of the nodes for fixing the state of exchange. The device consists (Fig. 1) of matching unit 1 and interface unit 2, functionally connected between itself and connected to the corresponding computer by wires 3 and 4 of the first and second inputs and buses 5 and 6 of the second and first outputs. The matching unit I comprises a control unit 7, an address generation unit 8, a command register 9, a switch 0, a state register 11, a first exchange state latching unit 12, a transmitter unit 13, and a transmitter / receiver unit 14. The interface unit 2 contains a synchronization node 15, information registers 16 and 17, a readiness signal generating node 18, a second exchange state latching node 19, a counter 20, a count register 21, and a comparison node 22; Control node 7 (Fig. 2) contains control register 23, the first group of elements And 24, the subscriber identification register 25, the switch 26, the element 27 and 27, the second group of elements 28 and the end of communication trigger 29. The address shaping node 8 contains (Fig. 2, the channel address register 30, a circuit 31 for comparing the address information of the channel with the information of the subscriber's address register 32. The readiness shaping node 18 includes a readiness trigger 33 and an AND 34 element. and contain (FIG. 3) parity control circuit 35, comparison circuit 36, exchange control register 37 and Element OR 38. Y-: the unit works as follows. In the initial state, when there are no boosters from the computer, the unit 1 does not respond I / O interface bus signals 4, and the interface unit 2 does not generate a ready or interrupted signal in the computer via buses 6. At the beginning of the communication session, a control word is transmitted from the computer, which can contain various information: the length of the array, the direction of information transfer, signs of information processing modes and etc. Before the exchange of information between the machines of the EC computer program and the M-6000 computer, they must be set up for the control words. For an example, consider the operation of the proposed device when the EC multiplex channel of the computer is connected to the direct access channel (efficiency P) computer M-6000. After the device’s address is multiplexed, the address code goes through the input buses 4 and node 14 to node 8 in register 30 to compare the address with the address code of the subscriber set for this device (matching unit 1). If the addresses match, the comparison circuit 31 resolves the response code of the subscriber's address from register 32 to switch 10, and through the switch, the ADR-K signal and the signals of the VBR-K channel and RVB-K channel signals go to the channel identification bus 23 to set the trigger RAB -A of this register and in register 25 for setting the ADR-A trigger in it. The signals RAB-A and ADR-A through the elements And 24 of node 7, the switch 10 and node 13 together with the code of the address of the subscriber arrive at the bus 5. In response to this, the channel exposes the read command code on buses 4 and the UPR-K channel identification signal, which, through switch 26, resets the ADR-A trigger and sets the UPR-A trigger in the register 25 and the trigger Continue in register 23, which through the first output of node 7 permits, using the command code from bus 4, set the trigger Read in register 9 commands. Register 34 through elements 24 to the second output of control unit 7 sets in state register I1 a zero status byte, which through switch 10 together with the subscriber identification signal UPR-A is fed to buses 5. Having received zero

the status byte, the channel terminates the sequence of the initial sampling signals by issuing the INF-K signal. Through the switch 26, the INF-K signal with the leading edge embraces the UPR-A trigger of register 25, and the falling edge with the RAB-A trigger of register 23. This finishes the initial sample and the channel is released for working with other external devices. In this case, the register 23, via the sixth control output, sets up the readiness trigger 33 of the node 18j which, through element 34, exposes the ready signal to the M-6000 computer. On the ready signal, the CAPP transmits a control word (two bytes) to the information register 16. A part of the control word, in which the array is located, enters the register 21, where it is remembered by the COOP signal (VP). Node 15 by the signal VP prohibits the ready signal on the element AND FOR, and through register 23 and switch 26 sets the trigger subscriber requirement (TRB-A.) In register 25. TRB-A signal through elements 24, switch 10 by bus 5 enters EC channel computers.

The multiplex channel on the TRB-A signal generates VBR-K and RVB-K signals, which through the switch 26, the address register 30 and the comparison circuit 31 open the address register 32, and the subscriber's address code enters the switch 10. At the same time, in modes 23 and 25 are set accordingly, the RAB-A and ADR-A triggers. Thus begins the sequence of I / O interface signals.

EC computer, entered by the subscriber, for data transmission. The channel, having received the subscriber’s address, generates a UPR-K signal, which through switch 26, when the trigger Continue register 23 is enabled, sets the INF-A trigger in register 25. The INF-A signal opens And through the 24 elements to Uat6p 10 to transmit the first byte of information from information register 16 to bus 5. In response to the INF-A channel, having received the information, again responds with an INF-K signal, with the leading edge of which the trigger 25 of the INF-A register 25 is zeroed, and the falling edge again sets the INF-A signal for transmitting the second byte of information from the information register 16. The channel again responds with an INF-K signal coming in through the identification bus. The channel to register 23 is used to generate permission to install the UPR-A trigger of register 25 through switch 26 and through elements 28 to install binds WU ended, The channel has finished in state register 11. Having received the final status byte, the channel to the UPR-A signal responds with INF-K signals, on the leading edge of which the trigger is reset. Read 9 commands in the register and UPR-A trigger in the subscriber signal identification register 25, and the RAB trigger is reset on the trailing edge. in control register 23.

Thus, the present invention provides the device performance performance by performing word counting of the transmitted array in the exchange process.

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FIG. 2

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Claims (2)

1. DEVICE FOR PAIRING by ed. No. 754403, with the proviso that, in order to increase the speed of the device, an account register, a comparison unit and a counter are introduced into it, and the first and second inputs of the counter are connected respectively to the second output of the unit synchronization and the fifth output of the control node, and the output with the first input of the comparison node, the output connected to the fifth input of the control node, the first and second information inputs of the account register are connected respectively to the outputs of the first information register and the node of the shapers-receivers, and the control input and output - respectively a seventh and output control unit. the second input of the comparison node. 2. The device according to claim 1, characterized in that the control unit comprises a control signal register, the group of inputs and the first input of which are the second and fourth inputs of the node, respectively, two groups of AND elements, the outputs of which are connected respectively to the fourth and second outputs of the node , switch, subscriber identity register, end of communication trigger. and element And, the first, second and third outputs of the signal register. the controls are the first, fifth and sixth outputs of the node, respectively, and the fourth, fifth and sixth outputs are respectively connected to the control inputs of the elements of the first group, the subscriber and switch identification register, the first and second outputs of which are connected respectively to the third and seventh outputs of the node, second the input of the signal register, control and information input of the subscriber identity register, the outputs of which are connected to the information inputs of the elements And the first group, the first information input is a switch It is first. the input of the node, and the second information input is connected to the third input of the node and the first input of the And element, the second input of which and the first inputs of the And elements of the second group are connected respectively to the seventh output and the group of outputs of the control signal register, the second inputs of the And elements of the second group are connected to the output of the trigger for the end of communication, the first and second inputs of which are connected respectively to the fifth input of the node and the output of the element I.