SU1173449A1 - Memory monitoring device - Google Patents

Abstract

A DEVICE FOR MONITORING MEMORY BLOCKS containing a control unit, a storage unit, an information I / O unit, a fault detection unit, a controlled power source and a thermal pressure chamber, the outputs of the first to fifth control units are connected respectively to the first inputs of the controlled thermal pressure chamber, the controlled source power supply, information input / output unit, accumulator and fault detection unit, the first output of which is connected to the first input of the control unit, and the second output - to the second input of the input / output unit information, the output of which is connected to the second input of the storage device, the output of which is connected to the second inputs of the information I / O unit and the controlled power source and thermal pressure chamber, the second outputs of the information I / O unit and the fault detection unit are one of the device outputs, the inputs of which are the second input of the malfunction detection unit and the third input of the information input-output unit, characterized in that, in order to increase the reliability of the control, a control clock generator is introduced into it x signals, a delayed delay unit, a switch and current drivers, the outputs of which are other outputs of the device, and the inputs are connected to the switch outputs, one of which inputs is connected to the output of the controlled delay unit, one of which inputs is connected to the output controlled clock generator and the second input of the control unit, clock generator input and other inputs of the controlled h block; hold-00 and switch are connected to the output of the “4 accumulators. four

Description

The invention relates to computing, in particular, to storage devices5 and can be used to conduct automated tests of memory blocks under conditions of destabilizing factors.

The goal of the isbret and i is to increase the reliability of the control during the testing of the memory blocks for increasing the volume of destabilizing factors that are studied in the process of testing.

FIG. A functional diagram of the proposed device is presented; Figs. 2-7 show, respectively, the operational circuits of the controlled clock signal generator, the controlled delay unit, KOf-iMyTaTopa, current driver, the control unit, and the fault detection unit.

The proposed device contains (FIG. 1) control block 1 drive 2, information input / output block 3, block of irregularities detecting block 4, control of power supply 5 controlled by a thermobarcamera 6, control of clock signal generator 7, block of controllable delay j switch 9 and shapers 10 currents. The device is connected to test object 1-1 (memory block),

The generator 7 contains (figure 2) a group of elements And 12 first binary counter 13, the oscillator 14 clock frequency and the first amplifier-generator 15,

The delay unit 8 comprises (FIG. 3) the second binary counter 16, the trigger 17f, the second group of elements AND IB, the element AND 19, the second amplifier-shaper 20 and the second clock frequency generator 21.

The switch 9 contains (figure 4} K elements And 22, where K is the number of connected formers 10 currents

The current conditioners 10 comprise (FIG. 5) K of transistors 2f3, base resistors 24 and 25 load elements, for example, resistors 26 and 27, power input 28 of transistors and input 29 of a neutral (zero potential bus),

The control unit 1 comprises (FIG. 6 a sync pulse generator 30 a single pulse generator 31, an address counter 32, a start address register 33, an end address register 34, a comparison block 35, an display element 36, AND 37-39 elements, OR elements 40 and 41 and switches 42.

The malfunction detection unit 4 comprises FIG. 7 an address counter 43, an address decoder 44, a loop signal generator 45, a modulo three convolution unit 46, a local control unit 47, a switch 48, an information input unit 49, a control information register 50, an error analysis block 51 and a sync generator 52.

The proposed device works as follows.

When the power is turned on, all units of the device are reset, and test program codes are entered into drive 2 through block 3. From block 1, the output of the counter 32 is transferred to the drive by the initial address. At this address, codes are selected from it, the corresponding bits of which, in the form of control potentials, go to power supply 5, thermal buffer 6, generator 7, delay block 8 and switch 9. The initial codes are such that the device sets the nominal test flight: nominal temperature, pressure, power, operating frequency of the test unit 11 (also known as the operating frequency of the control.), and the switch 9 provides for the disconnection of all the drivers 10, which can form in certain areas of the neutral and pytuemogo pulses to.ka unit serving for simulation of interference in block boundaries checks 4 are set emogo memory array and set the selected cyclic .vypolnenie test mode control unit 11.

After that, the device starts up. This is done by generating a single pulse, which from the output of the generator 3 through the element. MW 41 enters unit 4 and starts it. The monitoring of block 11 begins. As soon as the test of the specified memory array has been completed in block 4, the Start signal, which is intended to restart the monitoring of the specified array, is terminated by block 45. This signal enters block 1 and through the MBHTbi elements 38 and 40 to counter 32 as an addition to its contents. At this new address, from accumulator 2, a new test mode code is selected, which enters the aforementioned units and ensures that the test mode is updated under the new conditions. Unit 4 performs the control under these conditions and adds, in the above manner, +1 to the contents of the counter 32. This again provides for the next cycle of mode change, while monitoring the tested unit 11. If during the tests in the tested unit you turn out or a malfunction, then from the output of block 51 to block 1 the signal Fault. This signal enters the generator 30 and ensures the generation of a sequence of pulses, which is fed to block 3 to output to the external device the test mode code (from drive 2) and the fault address (from the output of block 4). After the output of these codes, the generator 30 triggers a pulse, which through the OR element .41 enters block 4 to start it after stopping due to a fault. This operation will continue until the comparison block 35 detects equality of codes in the counter 32 and register 34 in which the end is installed. address of the test program. This fact will mean that the execution of the entire test program has ended, and the indication element 36 will inform the operator. In addition, the potential from block 35 will prohibit the issuance of a system clock frequency from the output of element 37 to block 4. The device will stop working. The operator in the form of a printout of the external device will have data on the addresses of faults and test modes in which they occurred. In addition, the proposed device allows, using the switches 42, register 33 and unit 4, to set the required test mode to ensure the search for faults or the causes of them. . In the proposed device, in comparison with the prototype, besides the change in the supply voltages, temperature and pressure, the following destabilizing factors were introduced: the change in the operating frequency of the test block 11 and the simulation of noise and interference in the internal circuits of the test block. The change in the working frequency in the device is as follows. At the moment of changing the test modes, the generator 7 enters the input of a group of elements And 12 enters from accumulator 2 a code, the value of which determines the filling time of the counter 13. This code is entered into the overflow pulse counter, and the filling time of the counter is, in fact, the follow-up period frequencies. Thus, the frequency is controlled by a code that enters generator 7 from accumulator 2. Interference simulation is based on the principle of supplying neutral sections of the test block 11 with current pulses in separate parts of the electroplating network, causing interference and pickup in the inductively connected signal circuits. These pulses are produced by shapers 10, built according to the emitter follower circuit. Resistors 24-27 have correspondingly different values in order to obtain current pulses of various amplitudes. In the driver 10, the emitter repeaters are pairwise combined in order to be able to deliver current pulses of various amplitudes to a certain part of the neutral galvanic network. Using switch 9, two parameters for simulating interference are changed at once: the amplitude of the current pulse and the place of its supply. In addition to changing the amplitude of the current pulses and changing the sections of the neutral into which they are fed, the device allows you to automatically change the time of issuing a pulse simulating interference. This is accomplished by a controllable delay unit 8. Thus, the proposed device allows testing of memory blocks with increased reliability of control by taking into account the effect of additionally introduced destabilizing factors: changes in the operating frequency of the test unit and simulating interference that change their amplitude, time and place of occurrence according to the established dependence.

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Claims (1)

DEVICE FOR MONITORING BLOCKS OF MEMORY, comprising a control unit, a drive, an information input-output unit, a fault detection unit, a controlled power supply and a pressure chamber, the outputs from the first to fifth control units being connected respectively to the first inputs of a controlled heat chamber, a controlled power source, input block - output of information, a drive and a fault detection unit, the first output of which is connected to the first input of the control unit, and the second to the second input of the input / output inform block the output of which is connected to the second input of the drive, the output of which is connected to the second inputs of the information input-output unit and the controlled power supply and the pressure chamber. the second outputs of the information input-output unit and the fault detection unit are one of the outputs of the device, the inputs of which are the second the input of the fault detection unit and the third input of the information input-output unit, characterized in that, in order to increase the reliability of the control, a controlled clock generator is introduced into it, controlled delay, the switch and current drivers, the outputs of which are the other outputs of the device, and the inputs are connected to the outputs of the switch, one of the inputs of which is connected to the output of the controlled delay unit, one of the inputs of which is connected to the output of the controlled clock generator and the second input of the control unit , the input of the clock generator and other inputs of the controlled delay unit and the switch are connected to the output of the drive. SU „.1173449