SU1172049A1 - Digital device for phase-lock control - Google Patents

Abstract

- DIGITAL APPARATUS FOR FA base card locked loop, comprising a master oscillator, a phase discriminator which outputs are connected to respective adding inputs of subtracting the first down counter, characterized in that, in order to increase the accuracy of the phase locked loop, it introduced a second down counter, a RAKE delay line, the decoder, the first and second multiplexers and the counter, the outputs of which are connected to the corresponding inputs of the decoder, the outputs of which are connected to the first corresponding input The first multiplexer, the second inputs of which are connected to the corresponding outputs of the second reversible counter, the addition-subtraction inputs of which are connected to the corresponding transfer outputs of the first reversible counter, and: the regional outputs of which are connected to the corresponding inputs of the second multiplexer, whose information inputs are connected to the outputs of the multi-tap ( A delay line, the input of which is connected to the output of the first multiplexer, while the output of the master oscillator is connected to the input of the counter, and you od second multiplexer coupled to the control input of the phase discriminator. (uh 4 CO

Description

The invention relates to radio engineering and can be used in synchronization systems and coherents.

communication systems at a high frequency signal whose phase is being monitored.

The aim of the invention is to improve the accuracy of phase self-tuning.

The drawing shows a structural electrical circuit of the proposed device.

The proposed digital device .dl phase self-tuning contains the master oscillator 1, counter 2, decoder 3, the first multiplexer 4, the multi-tap delay line 5, the second multiplexer 6, the first and second revs: e counters 7 and 8, the phase discriminator 9.

The device works as follows.

The input signal coming from the device input is compared with the output signal recovered by the device in phase discriminator 9. At the input of phase discriminator 9, error signals are generated in the form of pulses, which are fed to the inputs of addition-subtraction of reversible counters 7 and 8. Reverse counters 7 and 8 control multiplexers 6 and 4, to the information inputs of which impulse sequences are received with different initial phases. At the inputs of multiplexer 4, pulse sequences with different initial phases are formed using a multiphase generator, which includes a series-connected master oscillator 1, a counter 2 and a decoder 3. At the output of the decoder 3, the pulse frequency

P f / Nc4, where is the pulse frequency of the master oscillator 1; Nj. (. - counter counting ratio 1 2 (difference of the initial phases of the pulse sequences at two adjacent outputs. Decoder 3).

The code at the outputs of the bits of the second reversible counter 8 permits the passage to the output of the first multiplexer 4 of a sequence of pulses with

corresponding initial phase, which is fed to the input of the multi-branch delay line 5. Multi-tap delay line 5 is made in the form of serially connected logic elements, the output of each of which is connected to the corresponding input of the second multiplexer 6. The total delay time of all logic elements 1 1 / f is determined by the delay time of the pulse sequence at the two nearest outputs of the decoder 3. Thus, the first reversible counter 7, together with the second multiplexer 6, performs the adjustment of the initial phase of the sequence of pulses coming from the output of the first multiplexer 4 within the delay time between the nearest pulse sequences. The phase quantization error at the output of multiplexer 6 is determined by the extrusion

LC,

where the counting coefficient of the reversible counter is 8, the Np coefficient is equal to the number of logic elements of the multi-drop line 5 delay. From the output of multiplayer 6, a sequence of pulses goes to the output of the device and simultaneously to the control input of the phase discriminator 9 for comparison with the input signal coming from the input of the device — to the information input of the phase discriminator 9. At the output of the device, a signal with a following frequency of output pulses is generated.

 . F f / Nc "

and maximum phase error

uV 360VNc4 + Npc

Obviously, the value of 1 / Npc characterizes the gain of the proposed scheme in comparison with the prototype.

The invention, unlike the prototype, allows several times to reduce the value of the phase error of the output signal.

Claims (1)

- A DIGITAL DEVICE FOR PHASE AUTOMATIC CONTROL, containing a master oscillator, a phase discriminator, the outputs of which are connected to the corresponding input of subtracting the first reversible counter, characterized in that, in order to improve the accuracy of the phase locked loop, a second reversible counter, a multi-tap delay line, a decoding line are introduced into it , the first and second multiplexers and a counter, the outputs of which are connected to the corresponding inputs of the decoder, the outputs of which are connected to the first corresponding inputs of the first multiplexer, the second inputs of which are connected to the corresponding outputs of the second reversible counter, the add-subtract inputs of which are connected to the corresponding transfer outputs of the first reverse counter, whose address outputs are connected to the corresponding inputs of the second multiplexer, the information inputs of which are connected to the outputs of the multi-tap delay line, input which 'is connected to the output of the first multiplexer, while the output of the master oscillator is connected to the input of the counter, and the output of the second multi plexora connected to the control input of the phase discriminator. »SU„ „1172049> 1 1172049 2