SU1171992A1 - Digital amplitude corrector - Google Patents

Abstract

A DIGITAL AMSHTUDA CORRECTOR containing the first adder, between the first and third inputs of which are connected the serially connected first and second delay elements, connected in series and included1 between the output and the third input of the first adder, the third and fourth delay elements, as well as the first and second multipliers, the outputs of which are connected to the fourth and fifth inputs of the first adder, respectively, and the third multiplier, with the first input and the output of the first adder being the input and output of the digital amp Corrective correction, respectively, characterized in that, in order to simplify the adjustment of the correction depth, a second adder is entered into it, the first and second inputs of which are connected to the outputs of the first and third delay elements, respectively, and the output is connected to the input of the first multiplier, the third adder, the first and the second inputs of which are connected to the output of the fourth delay element, the third input of the third summer of the torus is connected to the output of the third multiplier, and the output is connected to the input of the second slider, the fourth adder, the first input which is connected to the fourth input of the third adder and the output of the second delay element, the second input to the fifth input of the third adder and the input of the first delay element, and the output to the input of the third multiplier, the first, second, fourth and fifth inputs of the first adder, the first the input of the second adder, the first, second and third inputs of the third sum of the torus and the second input of the fourth summator G) are non-inverted: thin, and N3 the remaining inputs of the specified summers are inverting.

Description

The invention responds to radio and can be used in digital information processing systems. The purpose of the invention is to simplify the adjustment of the depth of correction. FIG. Figure 1 shows the structural electrical circuit of the digital amplitude corrector; in fig. 2 - its signal graph; on -fig. 3 - family of amplitude-frequency characteristics of the digital amplitude correction tioia. The digital amplitude corrector contains the first, second, third, and fourth elements 1–4 delays, the first, second, third, and fourth adders 5–8, the first, second, and third multipliers 9–11. Corrector works as follows. At low frequencies, adjacent samples are approximately equal for both input and output signals, i.e. at the output of each delay element, the samples coincide; therefore, the input samples compensate one another at the inputs of the fourth adder 8, at the inputs of the second adder 6, the input samples are compensated for the output. Input, samples arrive at the fifth and fourth inverting. the inputs of the third .go adder 7, and the output ones to the first and second non-inverting inputs of the third adder 7, therefore the output of this adder signal level is close to zero, since its third input does not receive a signal. Samples / arriving from the outputs of the second and fourth elements 2 and 4 delays, are compensated at the inverting third and non-inverting second inputs of the first sum of the torus 5. Since the fifth and fourth inputs of the first adder 5 do not receive a signal, only one is uncompressed the path from the output of the digital amplitude corrector to the first input — the first adder 5, therefore, the transmission coefficient of the device is close to one. At high frequencies, close to half the sampling rate, adjacent signal samples are equal and opposite, therefore, at the outputs of the second and fourth elements 2 and delays, the samples are equal to the input ones, and on the outputs of the first and third elements 1 and 3 delays are opposite to the input samples, therefore the input the readings and readings coming from the outputs of the delay elements compensate one another at the inputs of the fourth 8, second 6 and third 7 adders. At the inputs of the first adder 5, only the signal arriving at the first input of this adder from the output of the equalizer remains uncompensated. Therefore, at high frequencies, the transmission coefficient of the device is close to unity. At mid frequencies, the rise or collapse of the frequency response is determined by the output value of the signal of the third multiplier 11, and the range of corrected frequencies by the signal values of the first and second multipliers 9 and 10. Thus, the proposed device is an amplitude equalizer. Starting from the graph (Fig. 2), its transfer function in the α-plane is equal to ((I + CK-DA + B D-CK + DAIZ.S and U) D + in l Trg where K, B and A are the values of the third , the first and second multipliers are 11, 9 and 10 respectively. To estimate the frequency properties of the filter, we use the bilinear transform where c is the doubled sampling frequency. For this purpose, by means of this transformation, we transform the transfer function (1) into the p-plane. As a result, we obtain h (2-2A-B) p + 4KbgAp + o (2-2A + B),. Р- ((2-2АТвГ Hoped in the expression (2) 2-2А-В 332 Ч1 (2-2А + В) 2-2Л-В we have the transfer function - - 7 and / Р + К р + ир, Р t. FJf corresponding to the amplitude corrector. 3 From the analysis of the expression (3) it can be seen that in the proposed device (Fig. It is possible to adjust the shape of the frequency response using the coefficient K, which is 1171992-4 the area often produced in using the third multiply1) bodies, and the coefficients B and A determine this adjustment (Fig. 3).

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Claims (1)

A DIGITAL AMPLITUDE CORRECTOR, comprising a first adder between the first and second inputs of which are connected in series the first and second delay elements, connected in series and connected between the output and the third input of the first adder, the third and fourth delay elements, as well as the first and second multipliers, the outputs of which are connected to the fourth and fifth inputs of the first adder, respectively, and the third multiplier, and the first input and output of the first adder are input and output digital, amplitude o corrector, respectively, characterized in that, in order to simplify the adjustment of the correction depth, a second adder is inserted into it, the first and second inputs of which are connected to the outputs of the first and third delay elements, respectively, and the output is connected to the input of the first multiplier, the third adder, the first the second inputs of which are connected to the output of the fourth delay element, the third input of the third adder is connected to the output of the third multiplier, and the output to the input of the second multiplier, the fourth adder, the first input of which is connected the fourth input of the third adder and the output of the second delay element, the second input with the fifth input of the third adder and the input of the first delay element, and the output to the input of the third multiplier, the first, second, fourth and fifth inputs of the first adder, the first input of the second adder, the first , the second and third inputs of the third adder and the second input of the fourth adder are non-inverting, and the remaining inputs of these adders are inverting.