JPH0117289B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a waveform equalizer that equalizes signal waveforms.

Conventionally, there has been a device of this type as shown in FIG. In the figure, 1 is an input terminal, 2 is a delay line with a tap that serves as a delay circuit that delays the signal input to input terminal 1 by a predetermined time T (seconds) without attenuating it, and outputs the signal, and 3 is the delay line. 2 is an amplitude adjustment volume having a function of inverting the polarity of the signal output from the volume 3; 4 is an adder for adding the signal output from the volume 3; and 5 is for changing the phase of the signal output from the adder 4. A phase shifter 6 is an adder for adding the output signal from the phase shifter 5 and an output signal from one of the amplitude adjustment volumes 3, and 7 is an output terminal.

Next, the operation will be explained.

A portion of the signal input to the input terminal 1 is input to the delay line 2 with a tap, delayed by a predetermined time T (seconds), and output, and a portion is adjusted to an appropriate amplitude by the amplitude adjustment volume 3. Output. Next, a portion of the signal delayed by the predetermined time T (seconds) is similarly input to the delay line 2 with a tap, for a total of 2T.
A portion is input to the amplitude adjustment volume 3 and adjusted to an appropriate amplitude for a time T.
output as a delayed signal. In this way, the delay time of the tapped delay line 2 is all T.
Therefore, it was delayed by the time 0, T, 2T, ..., nT (n is the number of tapped delay lines) (n+1)
signals are output from the amplitude adjustment volume 3. Of these, n signals are added by an adder 4, phase-shifted by 0° or 90° by a phase shifter 5, and then output as an input signal to an adder 6 (hereinafter referred to as an echo signal). ). Further, the remaining one signal (hereinafter referred to as the main signal) is directly input to the adder 6 and added. Therefore, at the output terminal 7, a signal obtained by combining the main signal and the echo signal is obtained.

The above explanation is for the general case, but next, n=2
The case will be explained in more detail.

Figure 2 shows the block configuration of the conventional circuit when n=2, and Figure a shows the case where the phase shift value of the phase shifter is 0° (therefore, the phase shifter is omitted in the drawing).
Figure b shows the case where the phase shift value of the phase shifter is 90°.

In FIGS. 2a and 2b, 1 and 7 are input terminals and output terminals, respectively, 21 to 24 are delay lines with taps having a predetermined delay time T, 31 to 36 are amplitude adjustment volumes, 41 and 42 are adders, 51 is a 90° phase shifter, and 61 is an adder.

Now, consider the case where an extremely thin pulse is input to input terminal 1. However, it is assumed that the amplitude of the main signal is normalized to 1 by the amplitude adjustment volumes 32 and 35. That is, the amplitude values (tap coefficients) of the signals output from the amplitude adjustment volumes 31 to 33 are respectively a _-1 , 1, and a ₁ , and similarly, the amplitude values of the signals output from the amplitude adjustment volumes 34 to 36 are Let b _-1 , 1 and b ₁ respectively. FIG. 3 shows an example of the time response in the case of FIG. 2a. In this case, all three signals are in phase, and there is a time delay of T between each signal.

The frequency characteristics of each circuit in Figure 2 a and b are
Fa (f), Fb (f), Fa (f) = 1 + a _-1 e ^+j2 〓 ^fT +a ₁ e ^-j2 〓 ^fT = 1 + (a ₁ + a
_-1 ) cos2πfT−j (a ₁ −a _-1 ) sin2πfT……(1) Fb (f) = 1 + j [b _-1 e ^+j2 〓 ^fT +b ₁ e ^-j2 〓 ^fT ] = 1+
(b ₁ −b _-1 ) sin2πfT + j (b ₁ + b _-1 ) cos2πfT...(2), and the fluctuation terms of amplitude and group delay are respectively
(f) (dB), τ(f) (seconds), () a ₁ = a _-1 = b ₁ = b _-1 = k (|k|≪1) then Ga(f)≒17.372kcos (2πfT) τa(f)=0 (dB) (seconds) (3) Gb(f)≒0 τb(f)≒2kTsin(2πfT) (dB) (seconds)(4) () a ₁ = −a ₁ =k,b ₁ =-b _-1 =k(|k|≪
1) When Ga(f)≒0 τa(f)≒2kTcos(2πfT) (dB) (sec)(5) Gb(f)≒17.372ksin(2πfT) τb(f)=0(dB) (sec) (6), and the tap coefficient a _-1 , a ₁ (|a _-1 |= |a ₁ |)
Depending on the polarity of the amplitude characteristic or the delay characteristic, either the amplitude characteristic or the delay characteristic fluctuates in a cosine or sine shape, and the other does not fluctuate. The characteristics at this time are shown in FIGS. 4 and 5. Figures 4 and 5 show various characteristics of the circuits in Figures 2a and b, respectively, where a and d in both figures show the time response of the main signal and echo signal, respectively, b and e in both figures show the amplitude characteristics, respectively, Both figures c and f show group delay characteristics. The characteristics shown in FIG. 4 b and f are called cosine shapes, and the characteristics shown in FIGS. 5 c and e are called sine shapes. These characteristics can be used to equalize amplitude distortion or equalization distortion.

Conventional waveform equalizers are configured as described above, so when equalizing amplitude or group delay, only cosine or sine characteristics can be obtained, and the waveform equalizer This was inconvenient when designing.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by combining the conventional cosine type and sine type equalizers and weighting the tap coefficients in a specific relationship, the cosine equalizer It is an object of the present invention to provide a waveform equalizer that can obtain a cosine-shaped frequency characteristic that is horizontally shifted by a desired amount.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 shows a waveform equalizer according to an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same components as in FIG. is the output of the branch circuit 201.
90° phase shifter that shifts the phase by 90°; 301 to 304 are delay lines with taps that delay the input signal by a predetermined time T;
51 and 352 are the delay lines 30 with taps, respectively.
2,304 is an inverter/non-inverter selection circuit having a function of changing the phase of the output by 0° or 180°; 401 is an adder that adds the outputs of the inverter/non-inverter selection circuit 351 and the branch circuit 201; The above 90° phase shifter 202
and adders 501 and 502 that add the outputs of the inverter/non-inverter selection circuit 352;
are respectively weighted in a specific relationship and are amplitude adjustment volumes that adjust the outputs of the adders 401 and 402; 601 is the amplitude adjustment volume 50
1,502 and the output of the tapped delay line 301.

Note that the above circuits 301, 302, 351, 40
1, a first signal that forms a main signal obtained by delaying one of the outputs a of the branch circuit 201 by a time T, and an added echo signal obtained by adding the above output a and a signal obtained by delaying the output a by 2T or its inverted signal. The circuits 303 and 3 constitute a delay circuit network 8.
04,352,402, the phase shifter 202
A second delay circuit network 9 is configured to form an added echo signal from the output b of the .

The operation of the waveform equalizer configured as above will be explained with reference to FIGS. 6 and 7. However, since any signal waveform is expressed as a linear sum of extremely thin pulses, these extremely thin pulses will be treated as input signals below.

A signal with an amplitude of 1 input to input terminal 1 is divided into two by branch circuit 201, and one signal a is input to tapped delay line 301 having delay time T. A portion of the signal delayed by the time T by the tapped delay line 301 is input to the adder 601 without attenuation and becomes the main signal, and a portion is similarly input to the tapped delay line 302. After being delayed by a total of 2T, it is input to the inverter/non-inverter selection circuit 351. The output of the circuit 351 is added in an adder 401 to a signal with zero delay time that has not passed through the delay line 301, and is inputted to the adder 601 as an echo signal via an amplitude adjustment volume 501.

Further, the phase of the other output of the branch circuit 201 is rotated by 90° by a 90° phase shifter 202, and part of the signal b becomes an input to an adder 402 without delay, and a part is input to an adder 402 with a tap. After being delayed by a total of 2T via delay lines 303 and 304, the signal is input to an adder 402 via an inverter/non-inverter selection circuit 352 and added, and the output signal is amplitude-adjusted by an amplitude adjustment volume 502 and then converted into an echo signal. It is input to the adder 601 as . Therefore, output terminal 7
A main signal and two sets of echo signals are output.

Now, inverter/non-inverter selection circuit 3
In 51 and 352, non-inverter and inverter are selected, respectively, and the amplitudes are set to kcosθ ₀ and ksinθ ₀ respectively by amplitude adjustment volumes 501 and 502 (however, k and θ ₀ are constants, and k is an echo signal and the main signal, and θ ₀ is the amount by which the group delay or amplitude characteristic of this waveform equalizer is shifted in the horizontal direction on the frequency axis based on the cosine characteristic. Assuming that,
The transfer function F ₁ (ω) of the entire equalizer is F ₁ (ω) = 1 + 2kcos (ωT - θ ₀ ) ...(7) where ω = 2πf, and the amplitude characteristics and group delay characteristics G ₁ (ω), τ ₁
(ω) is G ₁ (ω) = 20log ₁₀ [1 + 2kcos (ωT - θ ₀ )] τ ₁ (ω) = 0 (dB) (second) (8). This characteristic is shown by solid lines in FIGS. 7a and 7b.
As can be seen from this figure, only the amplitude characteristic can be shifted in the horizontal direction (frequency axis direction) by an arbitrary frequency θ ₀ /T while the delay characteristic remains unchanged. θ ₀
When = 0, the characteristics are shown by the broken line in Figure 7a,
This corresponds to the case where a ₁ = a _-1 = k in Figure 2 a, and when θ ₀ = π/2, b ₁ = b _-1 in Figure 2 b.
It is clear that they match when =k.

Next, inverter/non-inverter selection circuit 3
Inverter and non-inverter are selected in 51 and 352, respectively, and the amplitude is adjusted by amplitude adjustment volume 501 and 502, respectively.
Assuming that the adjustment is made so that kcosθ ₀ and ksinθ ₀ , the transfer function F ₂ (ω) of the entire equalizer becomes F ₂ (ω)=1−j2ksin(ωT−θ ₀ ) ……(9), Amplitude and group delay characteristics G ₂ when k≪1
(ω) and τ ₂ (ω) are respectively becomes. This characteristic is shown by solid lines in FIG. 7c and d.
As can be seen from this figure, only the group delay characteristic can be shifted in the horizontal direction (frequency axis direction) by an arbitrary frequency θ ₀ /T while the amplitude characteristic remains unchanged.
Further, the characteristic when θ ₀ =0 is shown by a broken line in FIG. 7d. This corresponds to the case where a ₁ =−a ₋₁ =k in FIG. 2a.

In addition, although the above embodiment shows the case where one echo signal is used before and after the main signal, this is not limited to the case where only one echo signal is used.
Equalization can also be performed using a plurality of echo signals, and in this case, it becomes possible to equalize a plurality of frequency characteristics.

Further, in the above embodiment, the inverter/non-inverter selection circuit and the amplitude adjustment volume were constructed separately, but this can also be constructed with a single volume having a polarity inversion function. Further, the tapped delay line serving as the delay circuit may be replaced with a delay element such as a shift register or a cable, and furthermore, the branch circuit and the 90° phase shifter may be constructed with a 90° hybrid circuit.

As described above, according to the present invention, by combining a sine equalizer and a cosine equalizer and weighting the tap coefficients in a specific relationship, only either the amplitude or the group delay can be adjusted. There is an effect that the cosine-shaped frequency characteristic can be changed to a cosine-shaped frequency characteristic shifted by a desired frequency.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional waveform equalizer.
Figures 2a and 2b are block diagrams of the waveform equalizer in Figure 1 when the number of elements is small, Figure 3 is a diagram showing the time response waveform of the waveform equalizer in Figure 2a, and Figure 4 5 and 5 are diagrams showing frequency characteristics of an amplitude equalizer and a delay equalizer, FIG. 6 is a block diagram of a waveform equalizer according to an embodiment of the present invention, and FIG.
FIG. 4 is a frequency characteristic diagram of amplitude and group delay of the waveform equalizer shown in FIG. 201... Branch circuit, 202... Phase shifter, 8, 9...
First and second delay networks, 501, 502...
Amplitude adjustment volume (amplitude adjustment circuit), 601...
Adder. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A branch circuit that branches an input signal, and one output of this branch circuit that is delayed by a predetermined time T to create a main signal, and which is connected to the output of one of the branch circuits by a time 2T. a first delay circuit network that creates an echo signal by adding either the delayed signal or an inverted signal of the delayed signal; and a phase shifter that shifts the phase of the other output of the branch circuit by 90 degrees. a second delay circuit network that creates an echo signal by adding the output of the phase shifter and either a signal delayed by a time of 2T or an inverted signal of the delayed signal; and the echo signal and the main signal. _The first and second delay circuits first and second amplitude adjustment circuits that adjust the amplitude by weighting the echo signal output of the network with kcos θ ₀ and ksin θ ₀ ; the outputs of both amplitude adjustment circuits and the main signal output of the first delay circuit network; and an adder circuit for adding , and by adjusting the amplitude by the first and second amplitude adjustment circuits, the frequency characteristic whose group delay or amplitude characteristic is a cosine shape is shifted by a desired amount in the horizontal direction. A waveform equalizer characterized by: