JPS5812419A - Waveform equalizer - Google Patents

Abstract

PURPOSE:To improve the accuracy of equalization by inputting a delay-equalized signal to an amplitude equalizing circuit, and adjusting delay equalization and amplitude equalization independently. CONSTITUTION:An input signal from an input terminal 1 is supplied to the delay equalization part 11 composed of a delay circuit group 2, an amplitude adjusting circuit group 3 and an adder 4 to perform delay equalization. This delayed signal is branched by a branching circuit 30; one is supplied to a synthesizing circuit 16 through a variable delay circuit 31. The other branched signal is supplied to the amplitude equalization part 12 composed of a delay circuit group 13, an amplitude adjusting circuit group 14, and an adder 15 to perform amplitude equalization. This delay-equalized signal is sent to the synthesizing circuit 16, where the signal is synthesized with the delay-equalized signal. Thus, the delay equalization and amplitude equalization are adjusted independently, so accurate equalization is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention is a book relating to a waveform equalizer that equalizes a signal waveform, and particularly to a means for equalizing both the phase amount and the amplitude.

FIG. 1 is a block wiring diagram showing an example of a conventional waveform equalizer, in which (1) is an input terminal, and (2) is a plurality of terminals that delay the input terminal signal by a certain period of time without attenuating it and output it. A first delay circuit group consisting of tapped delay circuits (21)...(2n) connected in series; (3) is a means for inverting the polarity of the input or output signal of this tapped delay circuit and adjusting the amplitude; Il number amplitude adjustment circuit (3a) equipped with means for
... (3n) is a first amplitude adjustment circuit group, (4) is an adder that adds each output of this first amplitude adjustment circuit group, (
5) is an output terminal.

In the waveform equalizer configured as above, a part of the signal inputted to the input terminal (1) is sent to the tapped delay circuit (
2a) K input, delayed by a certain time T and output,
A portion is input to an amplitude adjustment circuit (3a), adjusted to an appropriate amplitude, and output. Next, the signal delayed by a certain period of time T is similarly partially inputted to the tapped delay circuit (2b), delayed by a total time of 2T, and outputted, and a portion is outputted to the amplitude adjustment circuit (3b). The signal is then adjusted to an appropriate amplitude and output as a signal delayed by a time T. Thus K and time 0, T.

2T, 3T...nT (Number of delay circuits with n-digit taps)
(n+1) signals delayed by 1 are added by an adder (4) and output from an output terminal (5).

The operation of the above waveform equalization amount will be described in more detail for the case where n=2. FIG. 2 is a block wiring diagram showing another example of a conventional waveform equalizer, and (1) to (5), (2g)
, (2b)=(3a) to (3e) are books showing the same or equivalent parts as the same reference numerals in the above tJL1 diagram.

In the waveform equalizer configured as above, the input terminal (
Consider the case in which an extremely thin pulse with an amplitude of 1 is input in 1). The amplitude values (tap coefficients) of the signals output from the amplitude adjustment circuits (3a) to (3c) are each a-1°1.11. Figure 3 shows the time response at this time.

Here, Figure 3 shows the amplitude adjustment circuit (3) of the waveform equalizer in Figure 2.
&) - (3c) are time response waveform diagrams.

In the figure, the signal with tap coefficient 1 is the main signal, and the tap coefficient a
The −1 and 1□ signals are called echo signals. If the frequency characteristic at this time is F(A, then F (f) = A
(1+a-, e″″J * M f T+ , 1.j
* M f t )=A(1+(a,+a−,)eo
s2g/T+j(at l-1-1)d'fT)...
...(1) where A is a constant. Letting the fluctuation terms of the amplitude and group delay characteristics be GV), dB, and τωsec, respectively, (1
)l, = am= k (1) when k < 1
When a□=-a-, =k (k<1), either the amplitude characteristic or the group delay characteristic exhibits a cosine-like movement, and the other remains an unchanging constant value. The characteristics at this time are shown in FIG. FIG. 4 is a time response waveform diagram and a frequency characteristic diagram of amplitude and group delay.

These characteristics shown in FIG. 4 can be used to soften the amplitude or group delay.

Generally, both amplitude and group delay are used to equalize signal waveforms.

Since it is necessary to equalize the amplitude and group delay, normally, as shown in FIG. 5, two of the circuits shown in FIG. 2 are used to separately equalize the amplitude and group delay. FIG. 5 is a block diagram showing yet another example of a conventional waveform equalizer.

(1) ~ (5) - (2a) - (2b), (3m) ~
(3e) indicates the same or equivalent parts as the same reference numerals in the above-mentioned figure tIIt1.

In the figure, (A) is a branch circuit that distributes the input signal from the input terminal (1) to the delay equalizer Q force and the convergence converter @;
) is a multiple tapped delay circuit (
13m) and (13b) are connected in series, a◆ is a plurality of amplitudes equipped with a means for inverting the polarity of the input signal Fiω force signal of this tapped delay circuit and a means for adjusting the amplitude. The second circuit consists of adjustment circuits (14m) and (14b).
In the amplitude adjustment circuit group, (c) is an adder that adds each output of the second amplitude adjustment circuit group, and α→ is a synthesis circuit that combines the output of this adder with the output of the adder (4).

In the waveform equalizer configured as above, vibration. Width adjustment circuit (3m) ”” (3e), (14a), (14
b) tap coefficient in order K a-1e1m@+lkl
+1)-1+1)1. Further K &, =&-1'
=ke a@ =1 * bl =b-1== k,
Then, equalization of one delay is possible by &l, and 11, and amplitude equalization is possible by b8 and b-1. A vector diagram of the input signal and output signal at this time is shown in FIG.

FIG. 6(1) shows that the output signal vector of the delay equalizer output has a phase difference θ1 from the branch circuit 00 output signal vector. Also, as is clear from Fig. 6 (It), is the output signal vector of the amplitude equalization section (b) pointing in the same direction as the output signal of the branch circuit (to)? The final output signal has a phase difference θ8 from the input signal vector. If amplitude equalization is performed after delay equalization in the delay equalization section (6), delay distortion will occur again. If this is done, amplitude distortion will occur again.

The conventional waveform equalization amount is configured as described above, so if the waveform distortion is small, the tap coefficient of the waveform equalizer can be small enough, and the amplitude and group delay can be adjusted almost independently. When the distortion is large, the approximation formula of K1l-1 (3) does not hold, so equalization of group delay generates amplitude distortion, and amplitude equalization generates delay distortion, and the independence of amplitude and group delay This method has the drawback that the accuracy is not maintained and the convergence during adjustment is poor.

This invention was made in order to eliminate the drawbacks of the conventional device as described above, and it provides a waveform equalizer that can adjust the amplitude and group delay independently by inputting the group delay equalized signal to the amplitude equalization circuit. The purpose is to obtain.

FIG. 7 is a block diagram showing one embodiment of the present invention, and shows (1) to (5), (2m), (2b) to (3a).
, (3b), 61~tx, (13a), (13b)
, (14m), (14b) Id The same reference numerals as in FIG. 5 indicate the same or equivalent parts. In the figure, Zeng is a branch circuit that branches the output of the equalization amount (4) into two, and (31) is a variable delay circuit that delays one of the outputs of this branch circuit for a certain period of time.

Considering the case where an arbitrary signal waveform is input to the waveform equalizer configured as above, the arbitrary signal waveform can be considered as a sum signal of extremely thin pulses, so in the following, the input signal of the thin pulse signal The case will be explained below.

FIG. 8 is a time response waveform diagram of each part when a thin pulse signal waveform is input to the waveform equalizer shown in FIG. 7, and the waveforms (1) to (a) in FIG. The waveforms of the parts with the same reference numerals are shown.

Part of the input signal of amplitude 1 inputted to the input terminal (1) K enters the tapped delay circuit (2a) having a delay time T, and the other part is inputted to the amplitude adjustment circuit (3a). A part of the output of the tapped delay circuit (2a) is input to the tapped delay circuit (2b) K having a delay time T, and the other part is input to the adder (4) K as is. Delay circuit with tap (2b
) is input to an amplitude adjustment circuit (3b) having a polarity inversion function. Let us now assume that group delay equalization is performed using the above configuration. The output amplitude of the tapped delay circuit (2a) is 1, and the output amplitude of the amplitude adjustment circuits (3m) and (3b) having a polarity inversion function is 1-1eJ, and a = -L.

= . The time response waveform diagram at this time is shown in Figure 8 (I).
.

(II). (1) indicates that an extremely thin pulse was input to input terminal (1) at K time 1 = 0, and ω
) shows the output time response of the adder (4). Depending on the magnitude of the tap coefficient kl, the group delay characteristic changes as shown in Figure 4 (II
), the delay amount changes with an amplitude of 2 and changes in a cosine shape at T. At this time, the amplitude characteristics are almost flat, but the adder (4
) The directions of the output signal vector and the input signal vector may or may not match, and there is a deviation in the phase angle θ as shown in FIG. 9 (1) K. Here, FIG. 9 is a signal vector diagram of the apparatus of FIG. 7. The pulse train shown in FIG.
31), and a portion is input to the amplitude equalizer (2) K.

The signal (pulse train) inputted to the amplitude equalization unit (2) is amplitude-adjusted by an amplitude adjustment circuit (14!L) having a polarity inversion function, and is input to the adder (2). The other part is a tapped delay circuit (13m) with a delay time T.

(13b), the amplitude adjustment circuit (
The order is adjusted in step 14b) and becomes the input to the adder (c).

If the tap coefficients of the amplitude adjustment circuits (14a) and (14b) at this time are b-□rb1, then in the case of amplitude equalization, b-1=
b, = , and its frequency characteristic Fi Fig. 4 (1)
As shown in , the amplitude of K fluctuates in a cosine shape with magnitude 2, and the group delay is flat, so amplitude equalization can be achieved by changing the value of . The time response waveforms at this time are as shown in FIG. 8a) to (to). FIG. 8 (The figure shows the output waveform of the amplitude adjustment circuit (14a), and the figure shows the output waveform of the amplitude adjustment circuit (14a).
14b) shows the output waveform, and (g) shows the output waveform of the adder α9.

One output of the branch circuit (to) is input to the variable delay circuit (31), is delayed by time T, and enters the synthesis circuit 0 peak.

It! 8rgI(V[), ■ indicates the time response waveform at this time. That is, @ is the time response waveform of the output of the variable delay circuit (31), and is the time response waveform of the output terminal (5).

Figure 9 shows the vector diagram at this time.

In other words, the output signal vector after amplitude equalization is oriented in the same direction as the input vector in the amplitude equalization section (6),
Since this is oriented in the same direction as the output signal vector from the delay equalizer α force, it is clear that amplitude equalization causes delay distortion.This indicates that equalization of amplitude and group delay can be performed independently.

In the above embodiment, the delay equalizer (11) and the amplitude equalizer (b) each use one echo signal before and after the main signal, but this example uses a plurality of echo signals. You can also equalize it. Furthermore, the same effect can be obtained even if the delay equalization section performs delay equalization using only the echo signal before or after the main signal, and the amplitude equalization section performs amplitude equalization including the amplitude distortion caused by this. I can wait. Furthermore, it goes without saying that in the delay equalization section and the amplitude equalization section, the delay caused by the group of tapped delay circuits can be replaced with a delay element such as a shift register to achieve the intended purpose.

In this invention, as described above, delay equalization and amplitude equalization can be adjusted independently by using the signal delayed and equalized in six ways as the input signal of the amplitude equalization circuit, so that accurate equalization can be performed. This has the effect of fast convergence in adjustment.

[Brief explanation of drawings]

Fig. 1 is a block wiring diagram showing an example of a conventional waveform equalization amount, Fig. 2 is a block wiring diagram showing another example of a conventional waveform equalizer, and Fig. 3 is a second waveform equalizer. 4 is a time response waveform diagram and a frequency characteristic diagram of amplitude and group delay, and FIG. 5 is a block wiring diagram showing another example of the conventional waveform equalizer. Figure 6 is a vector diagram of input signals and output signals, Figure tJ17 is a block wiring diagram showing an embodiment of the present invention, Figure 8 is a time response waveform diagram of the waveform equalizer of Figure 7, and Figure 9 is 8 is a signal vector diagram of the waveform equalizer of FIG. 7. FIG. In the figure, (1) is the input terminal, (2) is the first delay circuit group, (2a), (2b) is the delay circuit with LD tap, and (3) is the first delay circuit group.
(3a), (3b) are amplitude adjustment circuits, (4) is an adder, (5) is an output terminal, (to) is a second delay circuit group, (13a). (13b) a delay circuit with t-j taps, α♦ is a second amplitude adjustment circuit group, 09 is an adder, 0→ is a combining circuit, a branch circuit for {circle around (31)}, and (31) is a variable delay circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 6 Figure 7 Figure 8 Figure 9 Procedural amendment (spontaneous) 5. Commentary 1 Revised by the Commissioner of the Japan Patent Office 6 degrees. (3. Person who makes corrections
. . and 1. In formula (1), [a-,,-j2wfT J is replaced with "&-1@+jl
! ffT” and correct “,1゜j−πfT” as “,
1゜−j means πft, which is old as r + j (&*−a−
1) sin 2rfT J and aru wo -j (al-a
-1) Correct as sin 2rfT J. 2) r 8.6 in the upper row of formula (2) on page 4, line 13 of the same book
86 ks (2rfT) J toarwo r 8.686
X 2keos (2rfT) J Correct. 3) Page 6 of the same book, lines 8 and 9, “Machi=-a-8k
" is corrected to read ra1=-a-1=kIJ. 4) In the 7th line of page 7 of the same book, the words ``waveform distortion'' are corrected to ``cedar distortion.'' 5) In the 8th ft. 1st line of the same book, replace the phrase “equal stopper (4)” with “
Correct the statement "When the input signal is a thin pulse signal" to "When the input signal is a thin pulse signal". (7) On page 8, line 15 of the same book, the phrase ``amplitude adjustment'' is corrected to ``amplitude adjustment with polarity reversal function.'' (8) In the same book, page 9, line 14, ``Figure 7 (1) K is shown'' is corrected to ``Figure 7 (1) K is shown''. (9) On page 9, line 16 of the same book, ``Variable delay circuit 01 J'' is corrected to ``delay circuit 0 Y''. (G) On page 10, line 13 of the same book, the phrase "one output is a variable delay circuit" is corrected to "one output is a delay circuit." Ql) Same book, page 10, line 16 r (Correct the phrase "VD is a variable delay circuit" to "(capital) is a delay circuit.") (2) Added line, page 10 of the same book, "01 is a variable delay circuit."" is corrected to "0 power is a delay circuit." (To) Correct drawing No. 1 of the drawing as shown in the attached drawing. Q44 Drawing No. 6 is corrected as shown in the attached drawing. Correct as shown in the attached drawing. Correct αQ drawing Figure 9 as shown in the attached drawing. 7. Attachments (1) Corrected drawing Figure 1 1 copy (2) Corrected drawing Figure 6 1 copy (3) Correction Revised drawing Figure 7 1 copy (4) Corrected drawing Figure 9
1 letter (or more)

Claims (1)

[Claims] A first delay circuit group in which a plurality of delay circuits that delay an input signal for a certain period of time and output the delayed signal are connected in series.
A first adjustment circuit group comprising a plurality of amplitude adjustment circuits each having means for receiving an input or output signal of each delay circuit of the delay circuit group and inverting the phase of the signal and means for varying the amplitude; A first adder that receives and adds each output signal of the group, a branch circuit that receives the output of the first adder and branches it into two outputs, and outputs the first branch output of this branch circuit with a certain period of delay. a second delay circuit group in which a plurality of delay circuits are connected in series to delay the second branch output of the branch circuit for a certain period of time, and an input of each delay circuit in the second delay circuit group; A second adjustment circuit group consisting of a plurality of amplitude adjustment circuits each having a means for receiving an output signal and inverting the phase of the signal and a means for varying the amplitude; receiving and adding each output signal of the second adjustment circuit group; A waveform equalizer comprising: a second adder for adding a second adder; and a synthesizing circuit for synthesizing an output of the second adder and an output of the delay circuit.