SU1170603A1 - Device for generating logarithmic frequency series - Google Patents

Abstract

A device for forming a logarithmic frequency series containing a first binary counter, a second binary counter connected in series, a zero detector and a key block whose outputs are connected to the installation inputs of the second binary counter, the clock input connected to the clock pulse bus, characterized in that expanding the functionality of the device by reducing the base of the logarithm of the generated frequency range, an encoder and a serially connected impulse bus are introduced into it In terms of frequency change, a frequency counter, an octave counter and a switch, the first information input of which is connected to the detector zero output and the input of the first binary counter, the discharge outputs of which are connected to the other information inputs of the switch, respectively, the bits of the frequency counter bits are connected to the inputs of the encoder, you (l moves which are connected to the corresponding inputs of the block of the club.

Description

j The invention relates to a pulse technique. The purpose of the invention is to expand the functionality of the device by reducing the base of the logarithm of the generated frequency range. In FIG. 1 shows a block diagram of a device for generating a logarithmic frequency range; in fig. 2 - time diagrams of his work (g, g - in an enlarged scale). The device for generating a logarithmic frequency range contains the first binary counter 1, the second binary counter 2, the detector 3 zero, the block of 4 keys, the switch 5, the encoder 6, the counter of 7 frequencies, the counter of 8 octaves, the bus clock and pulse frequency changes, bus clock pulses, the second binary counter 2, the detector 3 zero and the block 4 keys are connected in series. The frequency change pulse bus, the frequency counter 7, the 8 octave counter and the switch 5 are also connected in series. The outputs of the frequency counter 7 are connected to the inputs of the encoder 6, the outputs of which are connected to the inputs of the 4 key block, the outputs of which are connected to the installation inputs of the second binary counter 2. The output of the zero detector 3 is connected to one of the information inputs of the switch 5 and the input of the first binary counter 1, outputs bits of which are connected to the remaining information inputs of the switch 5. The device operates as follows. Counter 2, detector 3, and block 4 form a controlled frequency divider, dividing the frequency of the input clock pulses (Fig 2a) by integers — the division factors. Each time the counter 2 in its counting process overflows and goes into the zero state, the detector 3 zero is triggered (Fig. 21)). At the same time, the pulse from the detector 3 output zero through the block 4 keys will force the transfer of counter 2 to a certain condition characterized by the number M. By changing the number M, you can change the number of allowed states of the counter, thereby controlling the division factor 03, change pulse frequency output divider 3 zero. The division factor K of the frequency divider is calculated by the formula K M, where n is the number of bits of counter 2. Since the setting of the bits of counter 2 is done at the moment of its complete zeroing, it is sufficient to use only the inputs of setting the bits of the counter 2 to 1. Switching the division factor (selection the numbers M) are produced by the commands of the 7 frequency counter, which calculates the frequency changing pulses. The period of frequency change pulses (Fig. 2o) is usually chosen to be much longer than the period of the pulses at the output of the detector 3 zero. The number of different division factors and, accordingly, the number of different pulse frequencies at the output of the detector 3 zero is equal to the number of possible states of the 7 frequency counter. Converting the binary code taken from the outputs of the bits of frequency counter 7 into the code by which the keys of block 4 corresponding to the specified division ratio are opened produces an encoder 6. The division coefficients are chosen so that in the process of filling the frequency counter 7 with frequency change pulses (Fig. 21 } the frequency of the pulses at the detector output 3 zero (Fig. 2o) increased stepwise according to a logarithmic law ranging from the value of f to 2f, returning to the initial value of f with overflow and zeroing of the frequency counter 7 (Fig. 29). At the same time, a periodically repeating series of frequencies with a small frequency range — twice — is formed at the output of the detector 3. Zero The base of this logarithmic series can be quite small and is ensured by the choice of the number of frequencies in the series D. The binary counter 1 calculates the pulses coming from detector output 3 is zero, produces a division of a number of frequencies. At the output of the first discharge of counter 1, a discrete number of frequencies occur with values from f / 2 to 2f / 2, at the output of the second discharge - from f / 4 to 2f / 4 and etc. 3 The minimum value of the frequency of pulses arising at the output of the last discharge of counter 1 can be calculated using the formula mcn - where m is the number of bits of the counter 1. Binary codes arising in the course of the bits of the counter 8 octaves in the process of counting with the counters 7 and 8 pulses of the frequency change are fed to the control inputs of the switch 5, which ensures a sequential connection to the output of the device signals (Fig. 2L) arising at the outputs of individual counter bits 1. Switching is performed so that in the process of filling the counter of 8 octaves, more and more high-quality outputs of the counter 1 are connected to the output of the device. The input signal of the counter 1 is connected to the output of the device, after which the counter The 8 octave chord overflows and the output of the device abruptly returns to the signal with the minimum frequency (Fig. 2). Thus, all counters of the device operate cyclically. At the beginning of the operation cycle, in the zero state of the counters 7 and 8, pulses with a frequency f are generated at the output of the detector 3 zero, and the signal from the high bit of the (t) counter t, i.e. signal with frequency f -f-. When filling counter 7, the frequency of the pulses at the detector 3 output often increases by a logarithmic law to 2f, and at the output of the device to the value at the time of overflow and zeroing of the frequency counter 7, the counter 8 octaves go to state 1, at which the switch 5 connects to the output of the device a signal coming from the output t-1 of the discharge of counter 1. At the output of the device, a signal appears at a frequency of -2f p 2 0 max, 034, i.e. at the moment of overflow of the counter 7 frequencies, a frequency jump at the output of the device does not occur. At the time of the next filling of the frequency counter 7 at the output of the device, the formation of a logarithmic frequency range continues with an increase in the frequency of the pulses to the value 2f IMOIKC 2 after which the frequency counter 7 overflows, the counter 8 octaves go to state 2, etc. The maximum frequency of the signal at the output of the device is formed when the counters 7 and 8 are completely filled. It is equal to 2f. This ends the cycle of forming a logarithmic frequency range at the output of the device. With the arrival of the next pulse of frequency change, the counters 7 and 8 are zeroed, the return to the beginning of the cycle occurs. A variant of the specific implementation of the device. Let counters 7 and 8 be chosen two-digit, i.e. may take four states. In this case, in a logarithmic frequency range with values from f to 2f, four frequencies should be contained. The coefficient (base of the logarithm) of such a logarithmic series can be calculated by the formula a, where q is the number of possible states of the counter of 7 frequencies. In this example, the base of the logarithm of the generated frequency range a 1,19. The frequency range is obtained as follows: 19. ,, 68f- (2O The accuracy of orming of the entire logarithmic frequency range depends on the frequency formation accuracy achieved during the device implementation. Frequency ratios can be obtained, for example, by dividing the clock frequency 40f into numbers — dividing coefficients 40, 34, 29, 24. In this case, the deviation from the logarithmic law does not exceed 2%. For simplicity, a case is given that a number of frequencies are formed by dividing frequencies so new impulses 6 to numbers - dividing coefficients 6 Received 1 HI frequency range {- ,, (2p has deviations from the logarithmic law lying within 20; To obtain division factors 6-3, counter 2 is chosen three-fold. Numbers M are equal M z - K ; M, 23-6 6 M, 3; Mo 4; M 5 The encoder 6 performs the following transformations of the codes (M,) (M) (M,) (M4) The encoder 6 is a ROM. However, the analysis of the presented code conversion shows that for this simple example, the encoder 6 can be made much simpler, in the form of a single verter. t apoVmx UftnyflbCSiS The number of bits of counter 1 is chosen to be one greater than the number of possible states of counter 8, i.e. For this example, counter 1 must be three bits. The minimum frequency of the pulses at the output of the device is p - L - f. f iViHH 2 2 8 The maximum frequency of the pulses at the output of the device is 2f. Thus, in the example, the device is shown to obtain a logarithmic frequency range with a base number, changing the frequency of the signal at the output of the device by a factor of 16, deviations from the logarithmic law not exceeding 20%. The accuracy of the observance of the logarithmic law can be significantly improved by increasing the frequency of clock pulses, for example, to 40 and choosing higher division factors, for example, 40, 34, 29, 24.

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Claims (1)

DEVICE FOR FORMING A LOGARITHMIC FREQUENCY SERIES OF FREQUENCIES, comprising a first binary counter, a second binary counter connected in series, a zero detector and a key block, the outputs of which are connected to the installation inputs of a second binary counter, the synchronizing input of which is connected to the clock bus, characterized in that, for the purpose of expanding the functionality of the device by reducing the base of the logarithm of the generated series of frequencies, an encoder and a series-connected pulse train of pulses are introduced into it there are frequencies, a frequency counter, an octave counter and a switch, the first information input of which is connected to the output of the zero detector and to the input of the first binary counter, the outputs of the bits of which are connected to the other information inputs of the switch, respectively, the outputs of the bits of the frequency counter are connected to the inputs of the encoder, the outputs of which connected to the corresponding inputs of the key block. (L with i