SU1170510A1 - Read-onlv storage - Google Patents

Description

The invention relates to computing and can be used to store information in microprocessor-based computing devices and in automatic control systems.

The aim of the invention is to simplify the permanent storage device (ROM) by "compressing | ₀ information" and eliminating memory elements corresponding to repeating characters 1 in X and Y coordinates and character interlaces 01 and 10 in the Y coordinate of the ROM matrix.

The greatest effect is achieved when storing binary-coded monotonic functions, some special codes used in the system20

max automatic control (Gray code, Lipell code, etc.), as well as corrective codes.

The drawing shows a diagram of a permanent storage device.

The permanent memory contains a generator of 1 clock pulses, a counter 2, the first 3 and second 4 decoders, the first - the fifth 5-9 numerical matrices, trigger 10, the first group of synchronous NRT-trigger 5® Hera 11, the elements OR 12, the second group of synchronous KZ-triggers 13, the first 14 and the second 15 elements And the outputs 16 of the device.

The array of 35 N binary numbers to be stored is recorded in Table. 1 in the form of a matrix N (rows) x «n (columns).

"Information compression" is carried out in accordance with the following 40 algorithm.

1. Characters 1 of the first line of the table. 1. write to the same position of table 2, containing N rows and η columns.

2. In table. 1, starting with the first 45 rows of the first column, analyze the characters in a sequential way downwards.

3. If in the first and second rows of this column there is a combination of the $ 0 nation of characters 01 or 10, then in the positions of the second character of the table. 2 write character 1.

Combinations of characters 00 and 11 are omitted. 55

4. Go to the analysis of the characters of the second and third rows of this column and perform the actions according to item 3.

5. Go over to the analysis of the next pair of symbols and perform actions on items 3 and 4 up to (Ν — 1) - and Ν-th lines.

6. Go to the analysis of the symbols of the next column and perform the actions according to paragraphs. 2-5 up to the nth column.

7. In table. 2 in rows, starting with the second, there are groups of three

and more than repeating characters 1, mark in each group the first (1 _M ) and last (1 _k ) characters and destroy all intermediate characters.

8. In Table 2, the columns, excluding the characters of the first line and the characters 1, included in the groups according to claim 7, distinguish groups of three or more repeating characters 1, note that in each group the first (1 _L ) and last (1 _M ) and destroy all intermediate.

9. Single and double (11) symbols of table. 2 left without indexes.

In tab. 1, for example, an array of 27 16-bit numbers is written.

The array in the "compressed" form is recorded in Table. 2

Subarrays of symbols 1, marked in table. 2, indices H, K, L and M, are written down, respectively, in the numerical matrix 6, 7, 8 and 9; subarray unmarked characters 1 - in the matrix 5.

The device works as follows.

The generator of 1 clock pulses produces frequency pulses £ _t , at which at the outputs of the first group corresponding to the lower digits of counter 2, p-bit address codes are formed along the Y coordinate, and at the outputs of the second group corresponding to the high-order digits of counter 2,-bit address codes on the X coordinate, which are fed to the inputs of the decoders 3 and 4, respectively.

According to the values of the address codes on the X coordinate, the outputs 1-Ν of the decoder 4 are consistently excited, corresponding to the numbers of numbers stored in the ROM, where N is the number of numbers in the array, N is 2 ^P.

According to the values of the address codes in the Y coordinate, the outputs of the 1-n decoder 3 are consistently excited, [corresponding to the numbers of digits / digits, where n is the digit capacity of the number, n “Ό. And when excited,

3

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for example, the first output of the decoder 4 is consistently excited by all

1-n outputs of the decoder 3.

In the initial state, the first group of triggers 11, the second group 5

trigger 13 and trigger 10 are in the "0" state.

Pulses corresponding to characters 1 of the first row of the table. 2, from the numerical matrix 5 arrive at the first input of the element 14.

At the second input of the element I 14, the signal from the first output of the decoder 4 acts during the whole time of reading the first number, and the pulses of the first number pass on the trigger 11, setting to the state “G those which are at the moment of arrival of the pulse synchronization with the decoder 20

3. The remaining triggers 11 remain in the "0" state.

With the arrival of the (n + 1) -th clock pulse, the second and first outputs of the decoders 4 and 3, respectively, are excited, and then the recovery of the second number begins.

From the output of the matrix 5, the pulse corresponding to symbol 1 of the second row of the first column of the table. 2, through the element OR 12 enters the T-input of the trigger 11 of the first discharge, which is in the state "O" * and sets it to the state 'Ί ".

The impulse corresponding to the 1d symbol of the second column comes from matrix 8 and sets the trigger 13 of the second digit to the state "1’ ’.

From its output, the pulse through the element OR 12 returns the trigger 11 of the second digit to the state “O”.

Further, up to the 16th digit inclusive, the signals from the outputs of the matrices 5–9 are absent (see tab, 2), and the corresponding triggers 11 retain the same states.

With the arrival of the (2n + 1) -th clock pulse, the third and first outputs of the decoders 4 and 3, respectively, are excited, after which the recovery of the third number begins.

The signals corresponding to the first, third, fourth, seventh, eighth, twelfth, fourteenth, fifteenth and sixteenth bits of the outputs of the matrices 5-9 are not issued, and the triggers 11 of the corresponding bits retain their previous state.

The trigger 11 of the second discharge on the corresponding clock pulse is switched to the state "1" (the previous state "O") by the pulse from the output of the trigger 13 of the second discharge, which is in the state "1".

The signal corresponding to the symbol 1 _{n of the} third row of the ninth column in the table. 2, from the output of the matrix 6, sets the trigger 10 to the state "1" and, using the clock pulses corresponding to the ninth, tenth and eleventh digits, sets the corresponding triggers 11 to the state "1". The impulse from the matrix 7, corresponding to the symbol 1c, the trigger 10 returns to the initial state.

Similarly, the recovery is made up to the ninth number, where the pulse from the output of the matrix 9; the corresponding symbol 1 _m in the second column of the table, 2, the trigger 13 of the second category returns to the state "O".

Further recovery of the array of numbers occurs in a similar way up to the 16th digit of the 27th number, after which the signal from element 15 returns the first group of triggers 11 to the initial state.

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Claims (1)

PERMANENT STORAGE DEVICE containing a counter, clock generator, the output of which is connected to the counter input, first and second decoders, inputs! which are connected accordingly to the outputs of the first and second groups of the counter, the first numeric matrix, the address inputs of which are connected to the outputs of the first and second decoders, the first group of triggers, the direct outputs of which are device outputs, the OR elements, the outputs of which are connected to the counting inputs of the corresponding triggers of the first group, differing by that, in order to simplify the device, it contains the second group of triggers, a trigger, two elements AND and the second, third, fourth and fifth numeric matrices, the address inputs of which are connected to the address inputs of the first numeric matrix, the output of which is connected to the first inputs of the OR elements and the first AND element, the second input of which is connected to the first output of the second decoder, the last outputs of the first and second decoders are connected to the inputs of the second element And, the outputs of the second and third numeric matrices are connected respectively to the unit and zero inputs of the trigger, the output of which is connected to the second inputs of the elements OR, the outputs four that and the fifth numeric matrices are connected respectively to the single and zero inputs of the second group of flip-flops, the outputs of which are connected to the third inputs of the corresponding OR elements, the outputs of the first and second And elements are connected respectively to the single and zero inputs of the first group triggers, the outputs of the first decoder are connected to the synchronizing, inputs of the corresponding triggers of the first and second groups. > 1170510 '2