SU1168972A1 - Hybrid intergating device - Google Patents

Abstract

A SAFETY INTEGRATING DEVICE containing the first and second integrators, the output of each of which is connected to the first inputs of the first and second comparators respectively, the output of the first comparator is connected to the data input of the first trigger, the switch, the first output of which is connected to the input of the first integrator, and the large-scale resistor, the first the output of which is an information input device, characterized in that, in order to improve the accuracy of integration, a reference current generator, a counter, three multiples are introduced into it a quadrler, four NOT elements, a second trigger, an AND circuit, the outputs of the first and second AND elements are information codes of the device, the second inputs of the first and second comparators are connected to the zero potential bus, the second output of the scaling resistor is connected to the information input of the switch, the second the output of which is connected to the input of the second integrator, the sign of the generator of the reference current generator is connected to the output of the first multiplexer connected to the control input of the second multiplexer a, the first input of the first element AND and the first element NOT with the first input of the second element AND, the code of the second multiplexer is connected to the first control input of the reference current generator and through the second element NOT to (L the second inputs of the first and second elements AND, the third inputs of which connected to the clock input of the device, connected to the input of the counter, the output of which is connected to the control input of the switch, the second control input of the reference current generator, the first input of the third element And through the third NOT lement to the first input of the fourth AND gate and with the control inputs of the first and third multiplexers, second inputs of the third and fourth AND elements podklgoche. the first and second outputs of the reference current generator are connected to the inputs of the first and second integrators, respectively, the output of the second comparator is connected to the data input of the second trigger and the first information input of the third multiplexer, whose output is connected to the first information input

Description

cut the fourth element NOT with the second information input of the second multiplexer, and the second information input of the third multiplexer is connected to the output of the first comparator, the output of the first trigger is connected to the first information input

the first multiplexer, the second information input of which is connected to the output of the second trigger, the outputs of the third and fourth elements of And are connected respectively to the synchronous inputs of the second and first. triggers.

The invention relates to hybrid computing and can be used in analog-digital computing systems and automation devices for long-term integration of an analog signal.

The purpose of the invention is to improve the accuracy of integration.

Figure 1 shows the functional diagram of the hybrid integrator in figure 2 is a functional diagram of a digital logic unit; FIG. 3 is a functional circuit of the reference current generator; in FIG. 4, the time diagrams at the corresponding points of the device (in FIG. 1, these points are indicated in Latin letters),

Hybrid integrating device (figure 1) contains two amplifiers

1 and 2 direct current (TOT) and two capacitors 3 and 4, two commits 5 and 6, first trigger 7, switch 8, large-scale resistor 9, information input 10 of the device, generator t1 reference currents (GET), digital logic unit 12 , the counter 13, the third element is NOT 14, the input 15 clock pulses of the device, the information outputs 16 and 17 of the device.

Digital logic unit 12 contains the first 18, third 19 and second 20 multiplexers, quarter 21, first 22 and second 23 elements NOT, trigger 24, first 25, quarter 26, second, swarm 27 and third 28 elements I. UPT 1 and capacitor 3 form the first integrator 29, and the UFT 2 and the capacitor 4 - the second integrator 30.

The generator 11 reference currents contains a switch 31, an amplifier 32, resistors 33 and 34, keys 35 {35, a decoder 36, transistors 37 and 38.

The device works as follows.

In integrators 29 and 30, the dual integration mode is alternately implemented. The order of integration is established by means of a logical variable b representing

output of the n-th bit of the counter 13. When the first integrator 29 is implemented the first integration (time intervals f-Q-t. and on the diagram d, Fig.4), and the second

integrator 30 is the second integration (time intervals tp-t and t, -t in diagram f, figure 4). The source of the integrated voltage at the same time through a resistor 9 and switch 8

connected to the input of the first integrator 29, the first output of the GET 11 is de-energized. The second output of the GET 11 is activated — the reference current of one or another direction flows in it (in

30, depending on the sign of the voltage at the output of the second UFD 2), which produces; reduces the voltage (in absolute value) to zero at the output of the second UFT 2. The value of U, which is the integral of the input voltage during the first integration is converted into the time interval tg-t ,. This interval is filled with clock.

40 pulses, the number of which is proportional to the integral of the input action during the time of the first integration. These pulses appear at the output 17 of the negative increment, since that is a sign of a negative integrating voltage. If, then the output pulses appear at the output 16 of the positive increment (time interval t, -t on the diagram s, figure 4). In the first integrator 29 a second integration is realized (time intervals tj-t: and on diagram d, 4), and in the second integrator 30 - the first integration (time intervals ti-t4 and tf-tg on the diagram f, fig.D). The source of the integrated voltage is through a resistor 9 and a switch 8 connected to the input of the second integrator 30, the second output of the GET 11 is de-energized, the first output of the GET 11 is activated. The process of the second integration in the first integrator 29 is identical to the above similar process in the second integrator 30, therefore in the interval of time tj-t- there appear pulses of negative increment of the input voltage integral, and in the time interval, pulses of positive increment of the integral input new voltage. An analysis of the principle of operation of the device shows that the first 29 and second 30 integrators alternately integrate the input action, which contributes to the continuous integration of the input signal, and transforms the increments of the input voltage integral into a sequence of pulses whose number and sign (output number) correspond to the increment value of the integral and the sign of this increment. Dp implementation of the above specified - the device operation algorithm requires a controlled GET-11. One of the variants of such a generator is depicted in FIG. 3 When the switch 31 is in the upper position and a positive polarity reference current is formed at the output of the GET 11 (in FIG. 3, this direction is indicated by an arrow). When switch 31 is in the lower position and a negative polarity reference current is generated at the output of the GET 11. The reference current is diverted to the appropriate output using a switch, which includes keys 35 1-354 decoder 36. Further, the following switch logic is adopted:, - closed key 35,,, - closed key Г%, L-0 , - the key is closed, 4 1 - the key 354 is closed. It is fixed with i when directing the reference current of the corresponding LY sign on the second output (since the second integration is in the second integrator 30), and on the first output. In addition, the reference current to the input of the first 29 and second 30 integrator (depending on the value of the signal b) can flow only during the stern integration time (at the same time), at other times the signal, while depending on the value of the signal b is closed or key 35, or key 35, which leads to a branch of the reference current to a common point of the device. Control signals p and q are formed in block 12. The principle of operation of block 12 is as follows. The trigger 7 and the trigger 24, which is part of the block 12, remember for the time of the second integration the sign of the output voltage. The first 29 and second 30 integrators respectively, (the first input of the flip-flops 7 and 24 is the data input, the second input is the synchronous input). The sign of the voltages at the outputs of the first 29 and second 30 integrators is entered into the triggers 7 and 24 during the first integration in the respective integrators 29 and 30 in the form of a certain value of the logical variables q and h, which are robbed by the first 5 and second 6 comparators respectively. The following relations are assumed: if d (f) 5.0, then q (h) 0, if d (f): O, then q (h) 1. The first multiplexer 18 translates the memorized value q or h (depending on the value of the signal c) to the first output of unit 12. At this output, a signal p is generated, which in GET 11 controls the direction of the reference current. So, with (the second integration goes in the second integrator 30), (the first multiplexer 18 translates the signal h from the output of the trigger 24), therefore. If during the first integration in the second integrator 30 the condition is fulfilled (time t in diagram f of figure 4), then (diagram j, figure 4). This means that: the reference current at the second output of the GET 11 is fed to the input of the second integrator 30, which is required to reduce the voltage at the output of the second integrator 30. Other situations that arise in the device can be analyzed by analogy. Multiplexers 19 and 20 together with the element NOT 23 form a signal q. Using the data from the previous example, the principle of forming the signal q can be explained as follows. The signal allows the h signal to pass through multiplexer 19 (from the output of the second comparator 6). This signal goes to the first and second (NOT 21) information inputs of the multiplexer 20. The signal, which acts on the control input of the multiplexer 20, allows the signal h to pass through the information input of the multiplexer 20 (i.e., without inversion), therefore. Analysis of the diagrams h and q (Fig. 4) in the time interval shows that the signal is for the entire time of the second integration in the second integrator 30. If, as is the case in the time interval, then the signal and the multiplexer 20 passes the signal h through the information input with inversion, therefore. Analysis of the h, p, q diagrams (Fig. 4) in the time interval shows that the signal during the entire time of the second integration in the second integrator

30. Thus, with any sign of the output voltage of the second integrator 30, the signal during the entire integration time in the second integrator 30, which corresponds to the algorithm of operation of the entire device as a whole. Block 12 functions in the same way and during the second integration in the first integrator 29, only the signals g and g are used as input. Elements And 25 and 27 provide the passage of clock pulses to the outputs of the device only during the second integration in the respective integrators 29 and 30. This is ensured by supplying the opening signal q through the element NO 23. The signal p determines the number of the output on which the clock pulses appear . When the element 27 is opened and the clock pulses appear at the output 17 of the device (output f), which is the output of the negative increment of the integral, the input action. When the element And 25 is opened, the clock pulses appear at the output 16 of the device (output s), which is the output of the positive increment of the integral of the input action. And elements 26 and 28 ensure the passage of pulses. Records respectively to triggers 7 and 24 during

the first integration in the respective integrators 29 and 30.

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Claims (1)

A HYBRID INTEGRATING DEVICE containing the first and second integrators, the output of each of which is connected to the first inputs of the first and second comparators, the output of the first comparator is connected to the data input of the first trigger, a switch, the first output of which is connected to the input of the first integrator, and a scale resistor, the first the output of which is the information input of the device, characterized in that, in order to increase the accuracy of integration, a reference current generator, counter, three multiplex are introduced into it ora, four elements NOT, second trigger, four elements AND, and the outputs of the first and second elements AND are information outputs of the device, the second inputs of the first and second comparators are connected to the zero potential bus, the second output of the scaling resistor is connected to the information input of the switch, the second output of which connected to the input of the second integrator, the sign input of the reference current generator is connected to the output of the first multiplexer connected to the control input of the second multiplexer, the first input the first element AND and through the first element NOT with the first input of the second element AND, the output of the second multiplexer is connected to the first control input of the reference current generator and through the second element NOT to the second inputs of the first and second elements AND, the third inputs of which are connected to the clock input of the device connected to the input of the counter, the output of which is connected to the control input of the switch, the second control input of the reference current generator, the first input of the third AND element and through the third element NOT with the first input m of the fourth element And with control inputs of the first and third multiplexers, the second inputs of the third and fourth elements of And are connected to the input of the device's clock pulses, the first and second outputs of the reference current generator are connected to the inputs of the first and second integrators respectively, the output of the second comparator is connected to the data input the second trigger and the first information input of the third multiplexer, the output of which is connected to the first information input and SU „„ 1168972 cuts the fourth element NOT with the second information input of the second multiplexer, and the second information input of the third multiplexer is connected to the output of the first comparator, the output of the first trigger is connected to the first information input of the first multiplexer, the second information input of which is connected to the output of the second trigger, the outputs of the third and the fourth elements And are connected respectively to the sync inputs of the second and first triggers.