SU1166103A1 - Device for calculating values of trigonometric functions - Google Patents

Abstract

1. A DEVICE FOR CALCULATING TRIGONOMETRIC FUNCTIONS, containing an m-bit register (where the device is 1-1), GU is a bit accumulator, a counter, a block of memory, an element NOT, and two computational units, each of which contains an input register, a group And, the first and second switches and the first and second adders, the first information inputs of which are connected to the outputs of the elements of the AND group and the first adder, respectively, the output of the input register is connected to the second information input of the first adder and information the input of the first switch, the output of the second adder is connected to the information input of the input register, the first inputs of elements AND of the group and the control input of the second adder of the first and second power modules are combined, the second inputs of the elements AND of the group of the first and second computing blocks are connected to the outputs of the first switches of the second and first computing blocks; the output of the first digit tn -digit register is connected to the control input of the first adder of the first computational unit and through the NOT element to the control input of the first adder of the second computational unit and control input of the m -discharge adder, the output of which is connected to the information input t - bit register, the outputs of bits from the fourth to the tth of which are connected respectively to the bits from the third to the (| n-1) -th first information input of the t-bit of the adder, m-and the first bit of the information input This is connected to the control input of the device, the installation input of which is connected to the installation inputs (L C in the O-bit register, counter, and the enable inputs of setting the input registers of the first and second computational units, the installation inputs of the input registers of which are connected respectively to the first and second parallel information a: the inputs of the device, the clock input of which is connected to the clock inputs of the input registers of the computing blocks, the t-bit register and the counter, the output of which is connected to the address The total input of the block, the memory whose output is connected to the second information input of the t-bit adder, the output of the counter is connected to the control inputs of the first and second switches of the computational computing unit, characterized in that, in order to increase the speed, a three-digit input is entered into it adder, modulo adder two and first and second code converters.

Description

information inputs of which are connected to the outputs of the second adders of the respective computing blocks; second information inputs of the second adders of which are connected to the outputs of the second switches, whose information passes are connected to the outputs of the first switches of the corresponding computing blocks; the control and clock inputs of the code converters are connected respectively to the counter output and clock the device input, the first and second serial information inputs of which are connected respectively to the third bit of the first information input and the control input of the three-bit adder, the first and second bits of the first information input of which are connected to the control input of the device, the outputs of the bits from the first to the third t-bit register are connected to the corresponding bits of the second information input of a three-bit adder, the outputs of the first and second bits of which are connected to the corresponding inputs of a modulo-two adder, the output of which is connected to the first inputs of the AND elements of each group The computing unit and the readout input of the memory unit, the outputs of the second and third bits of the three-bit summer are connected respectively to the first and second bits of the first information input of the PT-bit adder, the outputs of the code converters are connected to the output of the device.

2. The device according to claim 1, which is that each code converter contains the first and second multiplexers, an adder modulo two and a trigger, with the information inputs of the multiplexers connected to the information input of the code converter, the control input of which is connected to the control multiplexer inputs, the output of the first multiplexer is connected to the first input of a modulo-two adder, the second input of which is connected to the output of the second multiplexer and the trigger information input, the clock input of which is connected to the input of the converter code, the outputs of which are the outputs of the modulo two adder and the trigger.

The invention relates to computational technology and can be used in systems with pipelined bitwise data processing. A device for calculating trigonometric functions is known, comprising two registers, two adders and a control unit with corresponding connections. The operation of the device is based on the implementation of the Woldra algorithm with the correction of the result for each iteration of L. The disadvantage of this device is low speed, because at each iteration the vector is rotated by a double angle and the coordinates are multiplied by factors. The closest to the invention according to the technical nature is a vector coordinate calculator that contains two registers, four adders, four multipliers, two shifters, two groups of AND circuits, a control unit, and a decoder with corresponding links. The device calculates the sine function, the cosine of the argument represented by the parallel binary code for the number of clock cycles, equal to the number of bits n 2. The disadvantage of the known device is the low speed when using it in systems with pipelined bit data processing. for receiving code bits, n clocks for computing functions, and n clocks for transmitting the bits of the result of the calculations. Thus, the delay between the reception of the digit of the first digit of the argument and the formation

at the output of the first bit, the result is at least 2p cycles.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that in the device for calculating trigonometric functions, there is a t-bit register (where t-bit is the device), a t-bit adder, a counter, a memory unit, an element tO NOT and two computational units each of which contains input re-. the group, the group of elements I, the first and second switches and the first and second adders, the first information inputs of which are connected to the outputs of the elements of the group I and the first adder, respectively, the output of the input register connected to the second information input of the first adder and information 20 input of the first switch, the output of the second adder is connected to the information input of the input register, the first inputs of the AND elements of the group and the control input of the second totalor 25 of the first and second computing blocks are combined, the second the inputs of the elements And groups of the first and second computing units are connected to the outputs of the first switches of the second and first computing units, respectively; the output of the first bit of the t-bit register is connected to the control input of the first adder of the first computing unit. unit and through the element NOT - with the control input of the first adder of the second computational unit and the control input of the t-bit adder, the output of which is connected to the infor-40 by the formation input of the t-bit register, the outputs of the bits from the fourth to V- which is connected respectively with the bits from the third to. . (t-1) of the first information input 4S of the W-discharge adder, the T-th discharge of the first information1, the ion input of which is connected to the control input of the device, the installation input of which is connected to the installation inputs of O 50-register register, the counter and the inputs for setting the input registers of the first and second calculator-: ny blocks, the installation inputs of the input registers are connected, respectively, with the first and second parallel information inputs of the device, the clock input of which is connected

with clock inputs of input registers of computing blocks, t-bit register and counter, the output of which is connected to the address input of the memory block, the output of which is connected to the second information input of the t-bit adder, the output of the counter is connected to the control inputs of the first and second switches each computing unit, in addition, a three-digit adder, modulo two and first and second code converters, the information inputs of which are connected to the outputs of the second adders corresponding to Computational blocks, the second information inputs of the second adders of which are connected to the outputs of the second switches, the information inputs of which are connected to the outputs of the first switches of the respective computing blocks, the control and clock inputs of the code converters are connected respectively to the output of the counter and the clock input of the device, the first and second serial information inputs which are connected respectively with the third bit of the first information input and the control input of the three-digit sum Matora, the first and second bits of the first information input of which are connected to the control input of the device, the outputs of the bits from the first to the third T-bit register are connected to the corresponding bits of the second information input of the three-digit adder, the outputs of the first and second bits of which are connected with the corresponding inputs of the modulo two adder, the output of which is connected to the first inputs of the AND elements of the group of each computational block and the read enable input of the memory block, the outputs of the second and third the bits of the three-bit adder are connected respectively to the first and second bits of the first information input of the t-bit adder, the outputs of the code converters are connected to the output of the device.

In addition, each code converter contains the first and second multiplexers, a modulo two adder and a trigger, with the information inputs of the multiplexers connected to the information input of the code converter. the control input of which is connected to the control inputs of the multiplexers, the output of the first multiplexer is connected to the first input of the modulo two adder, the second input of which is connected to the output of the second multiplexer and the information input of the trigger, the clock input of which is connected to the clock input of the code converter whose outputs are outputs modulo two and trigger. FIG. 1 is a block diagram of the device; in fig. 2 and 3 - block diagram 1 of the code generator and the switch. The device for calculating the trigonometric functions contains a t-bit register 1, a t-bit adder 2, a three-bit adder 3, a counter 4, a memory block 5, an adder 6 modulo two, a HE element 7, computing blocks 8 and 9, converters 10 and 11 codes, inputs 12-18, outputs 19-22. Each computational block contains an input register 23, an adder 24 and 25, switches 26 and 27, a group of elements AND 28. Each code converter contains multiplexers 29 and 30, an adder 31 modulo two and a trigger 32. Each switch contains a group of multiplexers 33. Computation trigonometric functions in the proposed device, as in the known device, are based on the implementation of the Walder algorithm. To perform this algorithm, it is necessary to present the argument cf as a sum: cf.SL 5; aTctg2-, where 5; , -l; n is the number of bits of the argument. In contrast to the known device that works with parallel codes, the argument to the input of the proposed device comes in the form of a sequential code. Therefore, the values of 5j must be determined from more complex and -1 .i 1-. The basic equation: .518,., 2 .arctg2 i-O where Sq ,, i are the digits of the i-x bits of the argument code; R is the scaling coefficient. To solve this equation, an adder 3 and an adder 6 modulo two are entered into the device. The convergence of the definition process 5 provides with the expansion of the set of possible values of 5, with 5; eLl, O, -1. The occurrences of values are 6; 0 leads to the dependence on the argument of the value of the deformation coefficient of the vector K, for the Walder algorithm, equal to Kl (1 + 2). To eliminate this effect, in the proposed device, the algorithm of vector rotation at each iteration, by a double angle, is used. At the same time, on iterations for which 5; 0, the vector is not rotated, but its coordinates are multiplied by a factor (1 + 2). This eliminates the dependence of the deformation coefficient of the vector on the value of the argument. The deformation coefficient n-i 2 becomes K ... P (H2). Before starting the calculations, a code equal to is written into the register 23 of the second computational block 9, which allows to obtain the undistorted values of the trigonometric functions. To fulfill the indicated actions, the vector coordinates calculated by Wolder's equations are supplemented at each iteration with the following form:; where xj is the coordinate value before the vector is rotated by the angle л,,, if 5, jt О and а 1/4, if 5-0. The introduction of amendments of this type is provided by the appropriate connection of the second switch in the computing units. The two blocks 10 and 11 perform the conversion of the parallel codes of the calculated functions and the digits of the serial redundant binary code. This achieves the uniformity of for & g the presentation of information at the input and output of the device, which is necessary for its effective use in systems with pipelining of data. The device works as follows. A constant code O is fed to input 12 and information input 15 of the device. A constant code is supplied to the information input 16 of the device, n + H equal to .N (1 + 2) -036878, where n is the number of bits of the result of the calculations. According to the initial setup pulse. the input to the device 13, the register 1 is reset, the counter 4, the O code 15 is written to the register 23 of the computing unit 8, and the code from the input 16 is written to the register 23 of the computing block 9 (n-f4) a) calculation cycles. In each LM cycle (, 1, ..., p-1) the inputs i and 18 of the device are given the i-gb (starting from the highest) digit of the code of the tf argument in the redundant binary code with a fixed zap, and the weight of the older bit Yes code (equal to 1 rad. Digit 5 {p; each bit takes one of three values: 0.1, -1 which are encoded by two binary bits P q, as follows P (, 0 corresponds to S, 0 1, I ( ;. 0 corresponds to P, | ,,, 1, qq ,,; 1 corresponds to S (The bit of P (. Is fed to the input 17 of the device, the bit is to the input of 18. For all the bits of the argument code c are taken for n cycles. For this sign 4 - n-1 The reading is equal to: ti, 21 (.OC. In the next four cycles (, n + 1, n + 2, n + 3) required to complete the calculations, the O code is fed to the device input 17, which corresponds. In each iM cycle (, 5, ..., n + 3), at the outputs 19, 20 and 21, 22, the digits 5y and Sij, (the K-th bit () of the excess binary code of the sine and cosine of the argument Cf are formed, and the weight The first (most significant) bit of the code is 1. The digits and 5c of each bit take one of three values: O, 1, -1, which are encoded with two binary bits in the same way as the encoding of the digits of the argument. Each 1st computing cycle. (, 1, ..., n + 3) ends with the appearance of the 1st clock pulse at the input 14 of the device. For each 1st clock pulse, the counter code 4 is changed to +1, the code from its information input is copied to register 1, the codes from their first information inputs are copied to the registers 23 of the computing blocks 8 and 9, and the triggers 32 blocks 10 and 11 the codes are rewritten from the outputs of the multiplexers 30, after which the (1 + 2) -th calculation cycle begins. After the end of the (n + 3) -th cycle, the formation and issuance of consecutive n-bit codes of X and y codes of sine and cosine of the argument ends (p. The values of and y are equal to –1 –1 SX.K – 3 × 2 : 5u 2 to-j .to The process of forming the numbers of the sine and Koci-shus codes consists of three stages, performed, starting with, in parallel. The first stage is the transformation of the argument code, the second stage is the calculation of the functions sine, cosine with the formation the result in the parallel code and the third stage is the conversion of the parallel result codes into the numbers of the serial-excess Full-time binary code. The technical effect of the industrial application of the proposed device before the known one is to increase the speed of the conveyor random data processing. The known device, when used in the specified mode, has a delay of issuing the first bit of the result relative to the input of the first bit of the argument of at least 2p clock cycles, where the p-bit operands. In the proposed device, this delay is reduced to four clock cycles, and the delay does not depend on the width of the operands. Therefore, the proposed device allows to increase the speed of the calculation of trigonometric functions in pipeline data processing in n / 2 times. For example, when the speed is increased 10 times.

f {v.2

Claims (2)

1. DEVICE FOR CALCULATING TRIGONOMETRIC FUNCTIONS, containing n-bit register (where m is the bit capacity of the device), ηι-bit adder, counter, memory block, NOT element and two computing units, each of which contains an input register, a group of AND elements, the first and the second switches and the first and second adders, the first information inputs of which are connected to the outputs of the elements of the And group and the first adder, respectively, the output of the input register is connected to the second information input of the first adder and the information input ervogo switch, the second output of the adder is connected to the data input of the input register, the first input! elements And groups and the control input of the second adder of the first and second computing units are combined, the second inputs of elements And groups of the first and second computing units are connected to the outputs of the first switches, respectively, of the second and first · computing units; the output of the first bit of the w-bit register is connected to the control input of the first adder of the first computing unit and through the element NOT to the control input of the first adder of the second computing unit and the control input of the m-bit adder, the output of which is connected to the information input of the m-bit register from the fourth to the mth which are respectively connected with the bits from the third to (t-1) -th first information input of the t-bit adder, the mth bit of the first information input of which is connected n with a control input of the device, the installation input of which is connected to the installation inputs in 0 ”m-bit register, counter and input enable inputs of the input registers of the first and second computing units, the installation inputs of the input registers of which are connected respectively to the first and second parallel information inputs of the device, the clock input of which is connected to the clock inputs of the input registers of the computing blocks, the m-bit register and counter, the output of which is connected to the address input of the block. the output of which is connected to the second information input of the m-bit adder, the output of the counter is connected to the control inputs of the first and second switches of each computing unit, characterized in that, in order to improve performance, a three-digit adder is introduced into it, an adder modulo two and the first and second code converters SU 1166103 the information inputs of which are connected to the outputs of the second adders of the corresponding computing units, the second information inputs of the second adders which are connected to the outputs of the second switches, the information inputs of which are connected to the outputs of the first switches of the corresponding computing units, the control and clock inputs of the code converters are connected respectively to the output of the counter and the clock input of the device, the first and second serial information inputs of which are connected respectively о with the third bit of the first information input and the control input of a three-bit adder, the first and second bits of the first information input of which are connected to the control input of the device, the outputs of the bits from the first to the third w-bit register are connected to the corresponding bits of the second information input of the three-bit adder, outputs the first and second bits of which are connected to the corresponding inputs of the adder modulo two, the output of which is connected to the first inputs of the elements AND groups of each calculation the intelligence block and the read permission input of the memory block, the outputs of the second and third bits of the three-bit adder are connected respectively to the first and second bits of the first information input of the p-bit adder, the outputs of the code converters are connected to the output of the device. 2. The device according to p. ^ Characterized in that each code converter contains first and second multiplexers, an adder modulo two and a trigger, moreover, the information inputs of the multiplexers are connected to the information input of the code converter, the control input of which is connected to the control inputs of the multiplexers, the output the first multiplexer is connected to the first input of the adder modulo two, the second input of which is connected to the output of the second multiplexer and the information input of the trigger, the clock input of which is connected to the clock m input code converter, the outputs of which are the outputs of the adder modulo two and flip-flops.