SU1157548A1 - Linear approximator - Google Patents

Description

not connected with the control input of the first key, the output of the fourth clock pulse generator, is connected to the second input of the AND element and the second polling input perHC- f is the first 1 offset, Gth () whose output is connected to the information input (1, 1) -th three-channel demultiplexer, the first output (", j) of the three-channel demultiplexer (2, M-1,) D) is combined with the second output (" -1, j) -th and third output (f-2, j) -ro three-channel demultiplexers and is connected to the information input (f-1, j + 1) -ro of the three-channel demultiplexer, the length comparison unit contains the matator-subtractor of the length of the approximation segment, the group of elements OR, and the element OR, the first output (1, j) -ro () of the three-channel demultiplexer is connected to the first input of the th -th element OR of the group, the output of which is connected to the information input (JJ-J) TO the size of the adder-subtractor of the length of a segment of the approximation, the informative outputs of which are connected to the outputs

the length of the length of the approximator, and the sign output is connected to the installation input to zero of the first trigger, the third output (M, J) -th (, 15 three-channel demultiplexer connects to the second input of the jl-th element OR group and the V th input of the OR element of the length comparison unit whose output is connected to the installation input to zero of the second, trigger, the outputs of the second, third and fourth cycles of the clock generator are connected respectively to the installation input of the subtraction mode, the reset input and the installation input of the addition mode of the length-adder the approximation segment, the outputs of the tilt coefficient reversible counter are connected to the inputs of the memory unit, the outputs of which are connected to the inputs of the buffer register, the jth output of the input register is connected to the first and address inputs (", px (1 -, Y) of three-channel demultiplexers , / - and the output of the buffer register is connected to the second address inputs (, /) - x (T7M) of three-channel demultiplexers.

The invention relates to computing technology, information processing devices. The purpose of the invention is to increase speed. Figure 1 presents the block diagram of the approximator; 2 shows a functional block diagram of a line comparison; Fig. 3 is a functional block length comparison block; 4 is a functional block diagram of the control unit; Fig. 5 shows a cell condition map of accumulators; 6 shows graphs explaining the operation of the approximator; Fig.7 block diagram of the approximator. The approximator consists of a block 1 of memory, a block 2 for comparing lines, a block 3 for comparing data, an input register 4, a buffer register 5, and a block 6 for control. Input 7 is used for the initial value of the slope of the approximating straight line, input 8 is used to offset its starting point. input 9 is for the approximated curve as a sequence of single increments (Fig. 6). Input 10 is the start input of the approximator, output 11 is the output of the sync pulse issuing the slope factor, and outputs 12 are the D outputs of the distance of the approximation segment. The end of operation signal is output at output t3. The information inputs of the line comparison unit 2 are the inputs t4 and 15, the polling input 16 of the unit 2, the outputs 18 and 19 of the unit 2, the inputs 20-22 of the comparison unit 3, and its outputs 23 and 24, as well as the inputs 25 and 26 of the control unit b and its outputs are 17 and 27. Line comparison unit 2 contains (FIG. 2) the initial offset register 28 and matrix M) (N three-channel demultiplexers 29, where N is the number of bits and +1, D is the maximum deviation of the lines. 3 Block 3 compares the length of FIG. 3) with holding the adder-subtractor 30 of the length of the approximation segment, a group of 31 elements OR, the element 1 of the 32. The control unit 6 (FIG. 4) with holds a controlled clock pulse generator (GTI), a trigger trigger 34, an error sign trigger 35, keys 36 and 37, an OR element 38, an AND element 39, a driver 40, a slope coefficient register 41, a slope reversal counter 42. In control unit 6 (FIG. 4), the installation input into trigger unit 34 of switching on is connected to input 10 of the launch of the approximator. The direct output of the trigger 34 is connected to the start input of the GTI 33 and the first information input of the key 36, the control | which input is connected to the code of the third cycle of the GTI 33. The first output of the key 36 is connected to the output of the sync pulse of the approximator output and the polling input the slope coefficient register 41, the outputs of which are connected to the inputs 7 of the slope coefficient on the approximator and the information inputs of the reversible counter 42 of the slope coefficient. The outputs of the latter are connected to the information inputs of the tilt coefficient register 41. The inverse output of the activation trigger 34 is connected to the second information input of the first key 36, its second output is connected to the control input of the second key 37, the first and second outputs of which are connected respectively to the summing inputs, and to the subtraction input of the reversible tilt coefficient counter 42. The control input of the counter 42 is connected to the output of the OR element 38. The code of the fourth cycle of the GTI 33 is connected to the second input of the AND 39 element, and the output of the first cycle of the GTI 33 is connected to the first input of the OR 38 element and to the input of the unit of the trigger 35. the inverse outputs of the trigger 35 are connected respectively to the nepBbw and the second informational inputs of the key 37. The trigger output 34 of the trigger is connected to the first input of the AND 39 element, the output of which is connected to the third input of the OR element 38 of the control unit 484 lazy and with the output 13 of the end of work signal Ator. . In block 2 of the line comparison (Fig. 2), the information inputs of the initial bias register 28 are connected to the initial bias input 8 of the approximator. The first and second polling inputs of register 28 through a group of inputs 16 of block 2 and a group of outputs 17 of control block 6 are connected respectively to the outputs of the second and fourth cycles GTA 33. The second (- ("(Tm)) output of register 28 is connected to information inputs (, 1) of the three-channel demultiplexer 29. The first output (l, j) of the three-channel demultiplexer 29 (2, M-1, j 1, /) is combined with the third output (-1,}) and the third output (-2 , j) -ro of three-channel demultiplexers 29 and connected to the information input (-1, i + 1) -ro of a three-set, direct demultiplexer 29. First output (l, j) -ro (j 1 , N) three-channel demultiplexer 29 through the output 19 of block 2 of the line comparison 2 and the input 21 of block 3 of the length comparison are connected to the first input of the j-th element of OR of group 31. The third output (M, j) of the (j 1, N) three-channel demultiplexer 29 through the output 18 of the line comparing unit 2 and the input 20 of the length comparing unit 3 is connected to the second input of the Jth OR element of group 31 and the jth input of the OR element 32 of the length comparing unit 3. In addition, in block 3, the output of the jth OR element of group 31 is connected to the information input (Nj) -ro of the length of the approximator-subtractor 30 for the length of the approximation segment, the information outputs of which are connected to the outputs 12 for the length of the approximator approximation segment, and the sign output through the output 23 of the comparator unit 3 and the input 25 of the control unit 6 is connected to the installation input to zero of the trigger 34. The output of the OR element 32 is% output 4 of the unit 3 and the input 26 of the control unit 6 is connected to the installation input of the zero trigger 35. The outputs of the second, second and fourth cycles GTI 33 through groups The outputs 17 of the control unit 6 and the group of inputs 22 of the length comparison unit are connected respectively to the read mode setting input, the reset input and the input

setting the addition mode of the totalizer 30 of the length of the approximation segment. The output of the formt-grower is 40 people. A group of outputs 17 of the control unit 6 and a group of inputs 22 of the length comparison unit 3 are connected to the installation input of the unit of the subtractor 30 dpina of the approximation segment.

Vykoda reversible tilt coefficient counter 42 through the outputs 27 of the control unit 6 is connected to the inputs of block 1: the memory, the outputs of which are connected to the inputs of the buffer register 5,

The information {input inputs of the input register 4 is connected to the input 9 of the approximated curve. The 1st output of the input register 4 (J, 1, N) is connected through the input 14 of the line comparison unit 2, connected to the first address inputs (5J) (-1 jM) three-channel demultiplexers 29, and the J- and output of the buffer register 5 through the input 15 of the line comparison unit 2 are connected to the second address inputs (f, j) x (li jМ) of the three-channel demultiplexers 29.

Memory block I is a memory drive in which it is in a single state. TljL (.2K 1) -e r spontaneous cells (,) 5 where (the address of the accumulator is, and Р is the size of the counter 42, Thus, these codes depend only on the number of digits of the coefficient 4) of the slopes of the interpolating direct , but does not depend on its type and my dt, Pr. These codes are universal, and a Permanent Storage Drive can be used.

If each unit is assigned an X step, and a step. on Y do in the case: e, when this unit contains a unit, then for a-th we get a stepped one, which interpolates the direct one, which has a slope factor equal to a binary fraction of the form 0.00.,. 0 Where e / shchnitsa is on. (m place after zapyu.

A sequence of interpolating direct pulses, the slope of which is not a simple fraction, can be obtained by summing the described sequences. For example, for direct tilt

0,10110 it is necessary to add up the sequences written in the first, third and fourth addresses, i.e. at the same time, read these addresses in the manner that memory block 1 generates the entire sequence of interpolating pulses.

We will consider the approximator's work on a concrete example.

Let, then, the memory block 1, the buffer register 5, the input register 4 and the line comparison block 2 have 23 bits, and the adder-subtractor 30-24 bits, the counter 42 and the register 41 of the slope factor - 5 bits each. Let the maximum error be equal to two, then the number of bits of the register 28 initial offset, equal to the number of addresses of the block 2 comparison lines, is equal to five

Let the initial offset be 2 i.e. the unit is recorded in the first digit of the register 28. The approximable curve I is written into register 4 as a sequence of unit increments (Fig. 6). Since its total increment is nine, the number 0,01010 is written to the counter 42 as the initial value.

Next, a signal arrives at the trigger input 10 of the approximator, which sets the trigger trigger 34 to the unit. The signal from its output enables the operation of the GTI 33, which generates clock signals, starting from the first. In addition, at the output of the imaging unit 40, a setup signal is generated, which writes a unit to the high-order bit of the subtractor 30,

The pulse of the first clock stroke, passing through the element 38, enters the interrogation of the counter 42 (Fig. 7), as a result of which the number 0.01010 is rewritten into the register 41 and the second and fourth addresses of the memory block 1 are read. Register 5 records a 23-bit sequence of single increments, corresponding to a straight line with a slope of 0.0010 (sequence a, fig.6).

The second clock polled the register 28. An impulse from its first bit is fed to the corresponding three-channel demultiplexer 29 of the line comparing unit 2. Since the first bit of the sequences a and i are zeros, the pulse travels on

the second output of the demultiplexer 29 of the first bit of the first address of the block 2 and from there to the input of the demultiplexer 29 of the second bit of the first address (curve & FIG. 6). In the second §, the delta has one in the sequence f, therefore the pulse passes to the second address of block 2. In the third bit there is one in the sequence, hence the tQ pulse passes to the first address of block 2, and so on until the fifth digit, after which the pulse arrives at the output 18 of the block 2 of the center lines (Fig. 6). Thus, in this block, the path of the polling pulses repeats the error curve and is scanned where the absolute value error is greater than L s dan, the error case is negative, 2 @ mp pulse, is formed at the fifth output of the 18th group, enters on the group Vkhov 20 of the block 3 cf, the length of length (Fig. 3) and through the functional group 3.1 of the element OR to the input of the corresponding bit of the adder 30, and through the element OR 32 to the output 24.

Note that the bits of totalizer 30 are located in the reverse 30th order (top c, top head), i.e. the output of the last bit of block 2 is connected to the input of the lower bit of the adder-subtractor 30, the output of the penultimate bit of the block. 2 - jj to the input of the second bit of the sumator 30, etc. before the output of the first bit of block 2 (on the left of Fig. 2), which is connected to the input of the higher bit of the adder - subtractor 30.,

The length comparison unit 3 operates in the following manner.

The location, in which the error exceeds L, is remembered as a single S recorded in the corresponding register of the subtractor 3.0 -. In a further embodiment of the routing leg, the adder reader 30 is put into subtraction mode. If 5 the length of the segment in which the error is within the norm, s, increases, then the number that contains the unit in the lower order (lower than S5) is subtracted from the available numbers, and in, the result is a positive number, t . zero in sign demator subtractor 30

The interrogation of line comparing unit 2 (Fig. 7) is nullified and repeated; The summator-subtractor 30 is at this time transferred to the addition mode; therefore, the pulse from block 2 is recorded in adder-subtractor 30, and thus the new length of the approximation segment is memorized. Thus, the comparison unit 3 performs a comparison of the lengths of the current and previous segments of the approximation and remembers the current if it is more than the previous one, i.e. the best variant of the approximating direct is chosen, the fact that the current version is worse than the previous Chdlin, the error of which does not go beyond the permissible limits, has become less) indicates the appearance of a unit in the sign de sum of the subtractor 30.

Returning to the recorder, remember that as the initial setting of the subtractor 30, the unit is recorded in its most significant bit. From block 2 of the line comparison, the pulse arrives for the fifth time from the most significant bit. This occurs during the second Tact, which GTI 33 is fed to the input of the setting of the subtraction mode cy p atopa-subtractor 30.

Since the subtraction produced a positive number, the trigger 34 remains in the S unit state. The trigger 35 of the first character is set to one. When comparing the lines, the error goes beyond the lower boundary, the pulse is formed, the TC in the fifth volume of the group of outputs 18 and in, is input to the input 20 of unit 3. In this case, a pulse appears at the output of the I-UIH 32 element, which enters the input 26 block 6 and sets to zero the trigger 35,

Thus, the trigger 35 is the trigger of the sign of error. In this state of the triggers 34 and 35, the pulse of the third cycle from the output of the switch 36 is fed to the input of the switch 37, and from its input to the input of the subtraction unit 15 of the reversing counter 42, which changes the slope factor of the straight line, which is equal to 0.01001. In addition, the clock always zeroed the adder-subtractor 30. All this corresponds to the algorithm (Fig.7).

The fourth cycle (Fig. 7) carried out the second survey of block 2 comparing lines at inputs 16 (Fig. 2), but at the same time 9 adder-reader 30 of block 3 is in addition mode, as a quarter of it arrives at its input of setting addition mode Tick GTI 33 And since in the third tick the subtractor 30 is set to zero, there is a unit in the fifth of the highest bit. Next, the interrogation of memory block 1 follows again (Fig. 7) and in the buffer register 5, a sequence of one increments is recorded, corresponding to direct B on the graph ((X) (Fig. 6). When interrogating block 2, the pulse passes along the path The error fi exceeds the limits of the tolerance minus, therefore the signal from output 2A of block 3 sets trigger 35 to zero, and the number in the counter 42 of the slope factor again decreases by one and is equal to 0.01000. This corresponds to the variant (Fig. 6). Here the error goes beyond the positive therefore, the pulse from block 2 is fed to one of the inputs 21 of the group and does not generate a pulse at the output 24 of the block, compared to length 3. The trigger 35 remains in the single state and the pulse from the output of the key 37 increases from the counter of the slope coefficient 42 and equal to p 0,01001 In this case, when polling block 2 flo from the second clock from the number recorded in adder 30, more is subtracted, which leads to a change in the sign bit of summator 30 and, therefore, to 48 the appearance of a pulse at input 25 of block 6 and to set to zero the trigger 3. In As a result, the third clock cycle from the output of the key 36 is fed to the output 11 of the sync pulse issuing the coefficient of block 6 and to the polling input of the register 41 of the slope coefficient. At the same time, the contents of register 41, the previous value of the slope coefficient, is rewritten into counter 42. and is formed at the input 7 of the approximator for recording it to external devices. Switching the trigger 34 causes the fourth clock cycle from the output of the AND 39 element to output 13 of the approximation end signal and through the OR E8 element to poll counter 42. In addition, the same clock, as before, is polled by block 2 comparing lines transferring the subtractor 30 to the addition mode. The signal from the output 11 of the approximator yielded the best value found for the slope coefficient of the approximating segment contained in the register 41 and the slope coefficient counter 42, and the length of the segment represented in the positional code in the subtractor 30 can be read at any time after generating the signal output 13 approximator. Thus, for the four cycles of operation of the approximator (1b-th cycles), the maximum possible approximation line of the initial curve with a given error is determined and the parameters of the approximating segment are found.

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Claims (2)

A LINEAR APPROXIMATOR comprising an input register and a control unit, wherein the information inputs of the approximator are connected to the inputs of the input register, characterized in that, in order to improve performance, a memory unit, a buffer register, a length comparison unit and a line comparison unit are introduced into it, and the control unit contains tilt coefficient register, reversible tilt coefficient counter, two triggers, two keys, clock generator, AND element and OR element, and the approximator trigger input is connected to the set input The first flip-flop is connected to the first trigger, whose direct output is connected to the clock input * of the start pulse generator and the first information input of the first key, and the first output of the first key is connected to the sync pulse output of the approximator slope coefficient and the polling input of the slope coefficient register, the outputs of which are connected to the outputs approximator slope coefficient and information inputs of a reverse slope coefficient counter, the outputs of which are connected to information inputs, slope coefficient register, The rs output of the first trigger is connected to the second information input of the first key, the second output of which is connected to the control input of the second key, the first and second outputs of which are connected respectively to the summing input and the subtracting input of the slope coefficient counter, the control input of which is connected to the output of the OR element of the control unit , the output of the first cycle of the clock generator is connected to the first input of the OR element of the control unit and the installation input to the unit of the second trigger, direct and inverse the first outputs of which are connected respectively to the first and second information inputs of the second key, the inverse output of the first trigger is connected to the first input of the AND element, the output of which is connected to the second input of the OR element of the control unit and with the output of the approximator operation end signal, the line comparison unit contains an initial register displacements and a matrix of (where M = 2v. + 1, & is the maximum deviation of the lines, N is the number of bits) of three-channel demultiplexers, and the information inputs of the register of the initial offset are connected to the input of approximate bias of the approximator, the first input of the polling of the register of the initial bias SP m SP connected to the output of the second cycle of the clock generator, the output of the third cycle which is connected 1157548 is not connected with the control input of the first key, the output of the fourth cycle of the clock generator is connected to the second input of the element And the second input of the polling register of the initial offset, 1st (4 = 1, M) the output of which is connected to the information input of the (1, 1) -th three-channel demultiplexer, the first output of (♦, j) -g about a three-channel demultiplexer (<= 2, M-1, j = Tr3) is combined with the second output of the (i-1, j) -th and third output (l-2, j) -ro of three-channel demultiplexers and is connected to the information input (1-1, J + 1.) to a three-channel demultiplexer, the length comparison unit contains an adder-subtractor of the length of the approximation segment, a group of OR elements, and an OR element, and the first output of the (1, j) th (j = T, W) three-channel demultiplexer is connected to the first input / -th element of the OR group, the output of which is connected to the information input (Wj) -ro of the category of the adder-subtractor of the length of the approximation segment, information the outputs of which are connected to the outputs of the length of the approximator segment, and the sign output is connected to the input of the first trigger to zero, the third output of the (I, J) -th (1 = 1.15) three-channel demultiplexer is connected to the second input of the / -th element of the OR group and j ~ m the input of the OR element of the length comparison unit, the output of which is connected to the zero input of the second, trigger, the outputs of the second, third and fourth clock cycles of the clock generator are connected respectively to the input of the subtraction mode setting, the reset input and the mode setting input with dix adder-subtracter length segment approximation yields reversing the slope of the counter are connected to inputs of the storage unit, whose outputs are connected to WMOs. ". dams of the buffer register, the jth output of the input'register is connected to the first address inputs (i, j) -x (ί = 1, Μ) of the three-channel demultiplexers,) the th output of the buffer register is connected to the second address inputs (<', /) x (4 = T7M) three-channel demultiplexers.