SU1154257A1 - Device for preparing data for machines controlling processes of electron-beam micromachining - Google Patents

Abstract

DEVICE PREPARATION OF DATA FOR MACHINE CONTROL PROCESSES ELECTRON-BEAM micromachining, comprising an input unit of information, soy union of bilateral bonds with block firmware control, data outputs information input unit connected respectively to the data inputs of the memory unit, the address and control inputs of the memory are connected correspondingly with the address output and the control output of the write write permission of the firmware control unit, which is intended to increase fidelity and saving of memory by eliminating input information redundancy, a block for determining the blocking section of a topological figure is entered into it, the information input and output of which are connected respectively to the output and data input of the memory block, the operation control input is connected to the output of the operation of the firmware control block whose inputs are connected respectively with the output of the comparison result and with the outputs of the end of the cycle of operation of the block for determining the blocking of a section of a topological figure, moreover The block for determining the blocking of a section of a topological figure contains switches, groups of elements AND, groups of elements OR, registers, descrambler zero, node for performing operations of addition, subtraction, multiplication and compare, and a counter whose outputs of bits are connected respectively to the inputs of the decoder zero, the output of which is the output of the end of the block operation cycle, the information outputs of the first switch are connected respectively to the first inputs of the AND elements of the first (L and second groups, the outputs of which are connected respectively to The primary inputs of the first and second registers, the outputs of the bits of which are connected respectively to the first and second information inputs of the node for performing operations of addition, subtraction, multiplication, and division, the first output: the result of which is the output of the result of the block comparison, the second ND output of the result is connected to the information : the second input of the second switch, the outputs of which are connected respectively to the information input of the third register, with the first inputs of the OR elements of the first and second groups, the outputs of which are under lyucheny respectively to the data inputs of the fourth and fifth registers, the outputs of the bits of the third, fourth, fifth, sixth, seventh, eighth and ninth registers respectively connected to data inputs of lane

Description

the switch, the outputs of the bits of the sixth register are connected to the first inputs of elements of the third group, the outputs of the bits of the seventh register are connected to the first inputs of elements of the fourth and fifth groups, the outputs of the bits of the eighth register are connected to the first inputs of elements of the sixth and seventh groups, the outputs of elements AND of the third and sixth groups are connected respectively with the first and second inputs of the elements OR of the third group whose outputs are the information outputs of the block, the information inputs of the sixth ii of the seventh registers, the second the inputs of the OR elements of the first and second groups, the first inputs of the OR elements of the fourth and fifth groups and the installation input of the counter are connected respectively to the information inputs of the third switch whose information input is the information input of the block, the outputs of the elements of the fifth and seventh groups are connected respectively to the second and the third inputs of the elements OR of that group, the outputs of which are connected to the information input of the ninth register, the outputs of the elements AND of the fourth group are connected to the second inputs of the elements OR the fourth group, the outputs of which are connected to the informational input of the eighth register, the second inputs of the AND elements of the first, second, third, fourth, fifth, sixth and seventh groups, subtracting the counter input, enabling inputs of the first, second and third switches, run start input of the execution node The operations of addition, subtraction, multiplication, and comparison are connected to the control input of the block operation.

The invention relates to computing technology and can be used in digital machines for controlling electron beam microprocessing processes in the automated production of protective masks and photomasks for integrated circuits based on electron lithographic processes. A known digital machine comprising a control device, a transmitter unit, a memory device, an operation selection unit, a control table control unit, a coordinate axis alignment unit, a digital-analogue unit, a switch, a measuring transducer, and a comparison circuit. With the help of such a machine, the electron-beam installation in the part of the programmed beam movement over the substrate is carried out in order to create on its surface a topological microstructure of an integrated circuit with predetermined values of the technological modes of irradiation. Dunkyush sources for this large-scale when reproducing a topological microstructure pattern are the coordinates of the reference points of each of the elementary basic figures, the figure, the signs of the shape and its position relative to the coordinate axes, and some other service attributes of the DJ. The modern topology of the integrated circuit contains C8-110 elementary figures. , in connection with which it is necessary to enter a large amount of input information, which increases the number of operator errors when entering information into the machine, it presents you special requirements for the memory of the control computer. In addition, this leads to an increase in the operating time of relatively slow-acting and unreliable external devices, which negatively affects the performance of the process as a whole. Therefore, one of the important features of specialized tools designed to control electrolithographic {processes is the need to use a high-level input language in them, which facilitates the programming of technological tasks, increases the informative density of programs, and also simplifies the communication of technologists without control guide

by car. Such machines cannot operate with an input language of the required high level.

To simplify the programming process of the structures produced, a higher-level algorithmic language is used, becoming, between the process engineer and the control machine, a system for preparing data on a universal computer from among similar ones.

A digital machine is also known, which contains, in addition to the components indicated for the previous machine, a unit for the analysis of turns of the image p.

This machine implements a high level language, which greatly simplifies the programming process and reduces the amount of input information, especially for circuits with a periodic regular structure.

The closest in technical essence to the invention is a device for preparing control information included in a digital machine which contains a transmitter unit, a memory device, a control unit, a unit for determining the angular coordinates of the topological structure fragments connected to a code bus and control signal buses, a unit determine the coordinates of reference points and the type of basepieces of the figures connected to the code bus, the output of the block for determining the coordinates of the fragments of the topological structure and to the input of the control block W.

The machine has a mode for entering a description of complex topological figures in the form of coordinates of fracture points of a contour forming a topological figure. By virtue of the algorithm embedded in the machine structure, in order to carry out the process of splitting a complex topological figure into basic figures, it is necessary when describing a figure to specify points that break the convexity of the figure in the direction of the ordinate slaying. These points are vertices of the angle, the sides of which block the conduct of horizontal intersecting lines through the corner points of the contour of the topological figure, thereby preventing reliable coordinates of the elemental shapes to be cut. The need to fix points that violate the convexity of the topological

the figures leads to the impossibility of using the output of the computer aided design of the topology as input to the digital control machine, since the end product of the computer aided design of the topology is a geometric description of the outlines of the figures of individual templates. Thus, it is necessary to create a system of programs for converting the output information of the computer aided design system for the topology of integrated circuits into input information of a digital machine. But such an opportunity is not always available, moreover, for this it is necessary to attract highly qualified mathematicians and, finally, an indispensable condition is the availability of a universal computer. This leads to a lengthening of the design - manufacturing LSI cycle and to an increase in their cost.

The aim of the invention is to increase the reliability and save memory by eliminating redundancies (No bridges of input information.

This goal is achieved by the fact that, in a data preparation device for electron beam microprocessing process control machines, containing an information input unit connected by two-way communication with a microprogrammed control unit, the information outputs of the information input unit are connected respectively to the information inputs of the memory unit, the address and the control inputs of the memory unit are connected respectively to the address output and the control output of the write write resolution of the firmware control block, by entering The block for determining the blocking of a section of a topological figure, the information input and output of which are connected respectively to the output and to the data input of the memory block, the operation control input is connected to the output of the operation instruction of the microprogram control unit, the inputs of which are connected respectively to the output of the comparison result and to the end outputs the cycle of operation of the block definition blocking section of a topological figure, and the block block definition block definition of a topological gur contains switches, groups of elements I, g the ORP elements, the registers, the zero decoder, the unit for performing addition, subtraction, multiplication, and comparison operations and a counter, whose bit outputs are connected respectively to the inputs of the zero decoder, the output of which is the output of the end of the unit operation cycle, the information outputs of the first switch are connected respectively with the first inputs of elements of the first and second groups, the outputs of which are connected respectively to the information inputs of the first and second registers, the outputs of the bits of which are connected respectively to the first and The second information inputs of the node perform operations of addition, subtraction, multiplication and division, the first output of the result of which is the output of the block comparison result, the second output of the result is connected to the information input of the second switch, the outputs of which are connected respectively to the information input of the third register, with the first inputs of the OR elements the first and second groups, the outputs of which are connected respectively to the information inputs of the fourth and fifth registers, the outputs of the third, fourth, fifth, bits the sixth, seventh, eighth and ninth registers are connected respectively to the information inputs of the first switch, the bits of the sixth register are connected to the first inputs of elements AND of the third group, the outputs of bits (the seventh register are connected to the first inputs of elements of the fourth and fifth groups, outputs Rows of the eighth register are connected to the first inputs of the elements of the sixth and seventh groups, the outputs of the elements of the third and sixth groups are connected respectively to the first and second inputs of the elements OR of the third group, output The information inputs of the sixth and seventh registers, the second inputs of the OR elements of the first and second groups, the first inputs of the OR elements of the fourth and fifth groups and the installation input of the counter are connected respectively to information inputs of the third switch, whose information input is the informational input of the block, the outputs of the elements of the fifth and seventh groups are connected respectively to the second and third inputs of the elements of the OR of the fifth group whose 57 6 moves are connected to inf the ninth register's input input, the outputs of elements AND of the fourth group are connected to the second inputs of the OR elements of the Fourth group, the outputs of which are connected to the information input of the eighth register, the second inputs of the AND elements of the first, second, third, fourth, fifth, sixth and seventh groups, subtracting the counter input permitting the inputs of the first, second and third switches, the start input of the operations of the addition, subtraction, multiplication and comparison operations node are connected to the control input of the operation of the unit. FIG. 1 shows the structural diagram of the device; figure 2 is a fragment of the topological structure; Fig. 3 is a block diagram of the block definition blocking section of a topological figure; in fig. 4 is a block diagram of the firmware control block; FIG. 3 is a switch diagram; figure 6 - diagram of the pulse distributor; Fig. 7 is a diagram of a branch decoder; FIG. 3 is a diagram of the branch definition node; in fig. 9 - examples of angles, the sides of which block the horizontal secant; in fig. 10 - block scheme of the algorithm for determining blocking sections of a topological figure; in fig. 11-16 is a device operation algorithm. The device contains information input block 1, memory block 2, microprogram control block 3, block for determining the cross section of a topological figure block 4, switch 5, groups of elements AND 6-8 groups of elements OR 9-12, counter 13, registers 14-19, decoder 20 zero; switch 21, groups of elements AND 2225, group of elements OR 26, registers 27 and 28, node 29 of performing addition, subtraction, multiplication and comparison operations, switch 30, register 31, buses 32-47, distributor 48 pulses, node 49 branching, register 50, counter 51, fixed memory node 52, register 53, decoders 54-57, status indicator 58, communication buses 59-66, AND 67-70 elements, HE elements 71 and 72, tires 73- 79 links, elements 80-82, triggers 83-85, elements 86-89, tires. 90-100 links, decryptors 101 and 102, groups of elements 711 104, elements AND-STII 105 of NOT 103 and 107, element OR-NOT 108, buses 109143 of connection, elements AND-NOT 144-149; communication tires 150-154. As the node 29 can be used chip K155IG. The microcommand contains forty binary bits. The fortieth rank is c. control modulo 2. The 39th bit is marker. Units 3138 contain a micro-op code. Interregister transfers are divided into a separate group. For the transfer, the register number is indicated, from which the address information of the number must be taken, and the register register number — the address of the place. In order to represent the address in the microcommand, the number of digits from 25th to 30th is allocated, place addresses are allocated from 19th to 24th. The transition from one microcommand to another within the firmware field is accomplished by a system of conditional and unconditional jumps. To decide the sequence of operations, the firmware refers to status indicators, which are triggers and combinational circuits that capture signs of interchangeable states that reflect the intermediate phases of the processor. For analyzing the transitions, each condition of the firmware branch is matched to seven This code is located in bits 11-18 of the micro-instruction. In case of equality of the decrypted value of the branch code and the sign of the corresponding state indication, a conditional transition is made to the address specified in the address part of the microcommand (bit 1-10). Before starting work in block 2 of the memory, there is a description of the topological figure, represented by the coordinates of the corner points that are specified when walking around the outline of the figure in a clockwise direction. The point with the minimum ordinate at the minimum abscissa is taken as the beginning of the circuit detour. The internal contours forming the windows in the body of the figure, for example, the contour A, Bj, C, D, (figure 2 are defined by a separate; array; in the source data there is a number determined by the number of corner points of the figure’s contour reduced by 2 (N), 7 Before carrying out the process of dividing a figure into fragments and extracting basic shapes from them, the sections of the contour blocking the horizontal section are determined.The points that are the vertices of the angles whose sides are located in the 1st and 2nd quarter x an coordinate plane with the center of the coordinate system at the vertex of the corner (for example, the angles of the ABC in Fig. 9). The sides of these angles block the secant. The automatic detection of the vertices of these angles, the flow chart of which is shown in Fig. 10, is determined by determining the contour points of the polygon , the ordinates of which are less than the ordinates of neighboring points (for example, point D in Fig. 2). This condition is mandatory, but not sufficient. From Fig. 2, it can be seen that point I satisfies this condition, but the ZI and IR sides do not block holding secant. To establish uniqueness, the ratio of the abscissas of the points and their neighboring points is checked. In the case of ratios, Xg, x .., x. Point B is B A the apex of the angle whose sides block the secant. With other abscissa ratios, this statement is false. When the ratios x..x or, for an unambiguous answer, it is necessary to (about calculate the value of the expression Y8-UD) XB +. (CD-Xb) Y8 + UdXr-XdUd A negative value of this expression indicates that the point B belongs to the vertices of the angles whose sides block holding secant-. To perform these procedures, from memory block 2, under the influence of signals from microprogram control unit 3, applied to block 2, switch 5 via bus 32 to register 14 through the elements OR 10, the ordinates of the first are inserted into register 15 through the element OR 10 of the second description point contour (), and in counter 13 is the number N, which determines the number of corner points of the contour of the figure being processed, decreased by 2. In the next step, the values of the ordinates from registers 14 and 15 through the switch 21 and the elements 24 and 25 under the influence of control signals on tires 38, 41 and 42 skid sequentially with registers 27 and 28, respectively According to a control signal on the bus 44, the node 29 compares the contents of the registers 27 and 28. The result of the comparison is transmitted from node 29 via the bus 45 to the control unit 3. If the contents of register 27 are less than or equal to the contents of register 28, which corresponds to the state y y, the register 14 clears c (the buses for setting the operating nodes to zero state are not shown on FIG. 3), after which, under the influence of a signal supplied bus 34, through elements AND 7 and OR 9 enters the contents of register 15, then in register 15 of block 2 memory through switch 5, elements OR 10 enters the ordinate next in the description of the contour point Y, At the same time, the contents of the counter 13 under the influence of the signal supplied Bus 36 is reduced by one. Upon filling the register 15, the contents of registers 14 and 15, similarly to that described, are entered into registers 27 and 28, respectively, after which node 29 compares the contents of these registers, issuing the result of the comparison operation to microprogram control unit 3. If, at the comparison stage, node 29 outputs a signal corresponding to the fact that the contents of register 27 are greater than the contents of register 28 (in the next step, the value of the next in the contour of point y is entered into memory 16) At the same time, the contents of counter 13 are reduced. By entering information into register 16, the contents of registers 16 and 5 are successively transferred to registers 28 and 27, and then node 29 compares the contents of these registers. If they contain: 4th register 27 is more than the contents of the register (y) register The TA is cleared, and into it under the influence of a signal on bus 4 through the elements and 7, OR 9 the contents of register 15 are entered. In the cleared register 15, the signal on bus 35 through elements AND 8, SHIII 10 enters the contents of register 16, into register 16 of block 2 is the ordinate of the next point in the description of the contour of the point. Simultaneously with 115 10 carrying the ordinate from block 2 to register 16, the contents of the counter decrease by one. At the end of the filling operations of registers 14-16, the operations of repeating data from registers 15 and 16 to the node repeat 29 and their comparison in the latter. If the contents of registers 15 and 16 are equal, register 16 is cleared and entered into it from block 2 of the ordinate of the next point in the description of the contour, after which the operations of transferring data from registers 16 and 15 to node 29 and comparing them in the latter are repeated. If at the stage of comparing data from registers 15 and 16 the contents of register 16 are greater than the contents of register 15, when determining at the upcoming stages of operation of block 4, conditions under which the contents of register 15 are less than the contents of register 14 () in registers 17-19 of block 2 through switch 5 The elements OR 11 and 12 bring the abscissas of those points of the contour of the figure, the ordinates of which are stored in registers 14-16, respectively. After this, block 4 detects the ratio of the contents of registers 17 and 18, 18 and 19. Under the conditions: a) the contents of register 17 are greater than register 18, and the contents of register 18 are greater than or equal to the contents of register 19; b) the content of the 1st register 17 equals the contents of register 18, and the contents of register 18 is larger than the contents of register 19 — at the next step of operation of block 4, the contents of registers 14, 15, 17-19 are erased, and the contents of register 19 are affected by the control signal on bus 33 the elements 6 and 6 are entered into register 14, after which the next ordinate is entered into register 15 of block 2 and the operation of block 4 is repeated. Under the conditions: a) the contents of register 17 are equal to the contents of register 18, and the contents of register 18 is less than the contents of register 19; b) the contents of register 17 are smaller than the contents of register t8, and the contents of register 18 are smaller than or equal to the content of register 19 — the ordinate from register 5 and the abscissa from register 18 through elements 22 and 23 of School No. 26 under the control of squeeze signals on buses 39 and 40 are written sequentially in memory block 2 into an array of points blocking the holding of the secant. After this, the contents of registers 14, 15, 17 through 19 are erased, register 16 is entered into register 14, entered into register 15 from ordinate 2 of the next contour point, and operation of block 4 is repeated. The condition of equality of the contained registers 17 - 19 fixes the error of the initial data setting. Under the conditions of: a) the contents of register 17 are larger than the contents of register 18, and the contents of register 18 are smaller than the contents of register 19; b) the contents of register 17 is less than the contents of register 18, and the contents of register 18 is greater than the contents of register 19 — the expression (YyYy) Xb + (y, yy) x5 is calculated. + (Ub-Y5) x. The calculated expression is checked for sign. If negative, the point of the contour, the ordinate and the abscissa of which are stored in registers 15 and 18, respectively, are recorded as the point blocking the holding of the horizontal section. In the opposite case, the point is not fixed. To check this condition, the contents of registers 14 and 15 are transferred successively to registers 28 and 27, respectively, after which the signal on bus 44 node 29 calculates the difference of the contents of registers 28 and 27. The result of subtraction from node 29 through coke is 30 the signal on bus 43 is entered into register 31. After this, the registers 19 and 31 are sequentially entered into registers 27 and 28, respectively. In the next step, the node 29 calculates the product of the contents of registers 27 and 28. The result of the work through the switch 30, the OR element 12 is entered into the register 19. Then the registers 27 and 28 enter the contents of the registers 16 and 15, respectively. On a subtraction signal on bus 44, node 29 calculates the difference between the contents of registers 27 and 28. The result of this operation is transferred through switch 30 to register 31. After that, the contents of registers 17 and 31 are sequentially entered into registers 27 and 28, and by a multiplication signal, node 29 calculates em is the product of the contents of registers 27 and 28. The result of the product through the switch 30, elements SH1I 11 is entered into register 17. Next, in the same sequence, the difference between the contents of registers 14 and 16 and its product with the contents of register 18 is calculated. is entered in register 31. In the next steps of operation of block 4, the contents of registers 17 and 31 are recorded in registers 27 and 28, after which node 29, by the summation signal on bus 44, summarizes the received data. The result of the summation is transferred to register 31, after which the contents of register 31 in node 29 are summed with the contents of register 19. The result of the summation is entered into register 31. After that, the contents of register 31 are transferred to register 27, and register 28 is set to zero. According to the comparison signal on the bus 44, the node 29 compares the contents of the registers 27 and 28 and outputs the result of the comparison over the bus 45 to the microprogram control unit 3. If the calculated value is less than zero, the ordinate from register 15 and the abscissa from register 18 through AND elements 22 and 23, OR 26 are written sequentially to an array of points blocking (Holding assemblies of memory block 2. The end of block 4 is to set counter 13 to zero the state that is fixed by the decoder 20 and transmitted to block 3 of the firmware on bus 37. The effectiveness of the proposed device as compared with the known one is in reducing the amount of memory used for storing the original data, as well as increasing reliability of the input information by eliminating its redundancy.Thus, when the technologist technician input the initial data of the topology drawing describing the figure given in the example, 22 memory cells are used. For the same purpose, 26 memory cells are used in the known device. memory, even for such a simple example, is 4 memory cells, which is more than 15%. Under real conditions, the preparation of input information of a known device is carried out on data preparation systems, s using mainframes. Using the proposed device

115A257

allows you to reject such expensive systems.

Fig.1 5 Fi9.2

Fy

15

7274

77

76

70

77

69

79

87

3ft

jy. ,,

"7

five

I

i i I gtf

/ ri TTfТГГ

g, 1

J i 1 j i t

mm HI t t

i

one

I

I

I

I

Sri I I I Iff I 1

i i 1 t 1 I

t mm ra t gvv

 IfI1 I lk

  H / / iV - L Jfc

(

Hatfum

Find Totu Ordtash which menbshe ordinates neighboring moven

Yes

and .X -X 6 onucaHuL

Horses

to he mi / pa

ffpooepumb soshosheiiieHv X ,,

Try ratio

Not

Fixiashi

coordinates

Caused

A iys-ifAlXB i A-AB}

Not

Transmission 9an1 De & ampmpatS 8 register 27

Data transfer register / 6 8 peeucmpZB

Yes

Comparing duzle registers 27 and 2c

Not

abscissa of the point whose ordinate is about the register / 4

Data transfer register (5 in the register

Read 8 register 18 aScit, u € Cbt point, order ttomoifou 6

} f clearing register 15 feeucmpiiS

Lft. . Jw

t

Horses J

I

Z9 9t / H6 / x

tisak register

fHtieva lOHiMx petacmpa fte

Register Cleaning

Cvufwfawt yl 2 to register ffovefefma lrdimti

iuwtnemees cwofvioM l3e MlUAt {Nft-l)

W “M / UL

Claims (1)

DATA PREPARATION DEVICE FOR ELECTRON BEAM MICROPROCESSING PROCESSING MACHINES, containing an information input unit connected by two-way communications with the microprogram control unit, information outputs of the information input unit are connected respectively to the information inputs of the memory unit, the address and control inputs are connected to the memory inputs the control output of the permission to write reads of the microprogram control unit, which means that, in order to increase To save and save memory by eliminating input information redundancy, a block block for determining the cross section of a topological figure is inserted into it, the information input and output of which is connected respectively to the data output and input of the memory block, the operation control input is connected to the operation output of the microprogram control unit whose inputs connected respectively with the output of the comparison result and with the outputs of the end of the cycle of the block definition block section of the topological figure, and the block is determined The section locking section of a topological figure contains switches, groups of AND elements, groups of OR elements, registers, a zero decoder, a node for performing addition, subtraction, multiplication, and comparison operations, and a counter whose discharge outputs are connected respectively to the inputs of the zero decoder, the output of which is the output of the end of the cycle unit operation, information outputs of the first switch are connected respectively to the first inputs of the elements And of the first and second groups, the outputs of which are connected respectively to the information inputs and the first and second registers, the outputs of the discharges of which are connected respectively to the first and second information inputs of the unit for performing the operations of addition, subtraction, multiplication and division, the first output of the result of which is the output of the result of the comparison of the block, the second output of the result is connected to the information input of the second switch, the outputs of which are connected respectively with the information input of the third register, with the first inputs of the OR elements of the first and second groups, the outputs of which are connected respectively to the information the fourth and fifth register inputs, the outputs of the third, fourth, fifth, sixth, seventh, eighth and ninth register bits are connected respectively to the information inputs of the first switch, the outputs of the sixth register bits are connected to the first inputs of the And third group elements, the outputs of the seventh register bits are connected to the first inputs of the elements of the fourth and fifth groups, the outputs of the bits of the eighth register are connected to the first inputs of the elements of the sixth and seventh groups, the outputs of the elements of the third and sixth groups with are connected respectively to the first and second inputs of the OR elements of the third group, the outputs of which are the information outputs of the block, the information inputs of the sixth and seventh registers, the second inputs of the OR elements of the first and second groups, the first inputs of the OR elements of the fourth and fifth groups and the meter installation input are connected respectively information outputs of the third switch, the information input of which is the information input of the unit, the outputs of the elements of the fifth and seventh groups are connected respectively to the second the third inputs of the elements of the fifth group, the outputs of which are connected to the information input of the ninth register, the outputs of the elements of the fourth group are connected to the second inputs of the elements of the fourth group, the outputs of which are connected to the information input of the eighth register, the second inputs of the elements of the first, second, third, fourth , fifth, sixth and seventh groups, subtracting the counter input, allowing inputs of the first, second and third switches, the start-up input of operations of the node for performing operations of addition, subtraction, multiplication and comparable tions are connected to the operation control block entry.