JPS6046828B2 - Placement determination device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a placement determining device, particularly a method for determining the placement of logic gates on an LSI chip, the placement of ICs on a printed circuit board, etc., in an extremely short time compared to conventional software-based methods. The present invention relates to a placement determining device that makes decisions on time.

In the layout design of an LSI, what is the relative positional relationship between the multiple logic gates to be mounted on the LSI chip, or in the design of an IC printed circuit board, how should the multiple logic gates to be mounted on the printed circuit board be arranged? The design process of deciding where to place an IC on a board is called layout design for LSI and layout design for printed circuit board, respectively.

This layout design has a great influence on the success or failure of the subsequent wiring design.

In other words, if a good placement is given, a logic circuit in which 100% of the wiring routes can be found can be obtained, whereas if a bad placement is given, no matter how hard the wiring design is made, 100% of the wiring paths cannot be found. occurs often. Therefore, layout design has become an important design process in the design of printed circuit boards and U-chips. This placement design was often done manually, but recently it has been decided by a program using a computer with the aim of shortening design time, improving placement quality, and reducing design errors. A lot of things have happened. When processing placement design using software, a placement method called the replacement improvement method (or sequential improvement method) is often used to obtain a high-quality placement.

This method starts from a given initial configuration and starts with the parts (
The arrangement is gradually improved by replacing logic gates in the case of LS■ and ICs in the case of printed circuit boards. The criteria for determining whether or not the arrangement will be improved if the bare parts of a certain part are replaced are called placement evaluation criteria. As this evaluation standard, a standard called total wiring length minimization is used.

This criterion is used to evaluate a certain layout by temporarily drawing wires between components according to logical connection relationships, and assuming that the sum of the lengths of these wires is short, it is a good layout, and if it is long, it is a bad layout. (Here, ゜゜Temporary wiring゛ means to draw wiring that takes into consideration whether the wiring will short-circuit or not. Therefore, all wiring routes are drawn to be the shortest possible.) In the replacement improvement method, if you temporarily replace bare components selected according to a certain rule, reroute the wiring related to those components, and judge that the sum of the total wiring lengths mentioned above becomes smaller. The arrangement is improved by actually replacing the component bears and repeating this operation for different component bears in sequence, such as not replacing them unless they become smaller. The arrangement improvement procedure using the replacement improvement method will be explained in detail with reference to FIGS. 1 to 3.

FIG. 1 is an example of an initial arrangement. Here, it is assumed that the parts of one hat are arranged on a 4×4 array. The lines between the parts represent temporary wiring, and the quality of the arrangement is evaluated based on the sum of the wiring lengths. The wiring length is, for example, ``1'' between components 6 and 10, 1'' in the X direction and 2'' in the Y direction between components 1 and 2, giving a total distance of 3''. If the total wiring length sum in FIG. 1 is calculated using this method of calculation, it will be ゜゜54゛. Rearrangement is performed to decrease this value. For example, if parts 6 and 10 in Fig. 1 are replaced, the arrangement shown in Fig. 2 is obtained, but at this time, the total wiring length is
49゜, which means that the arrangement has been improved. By repeating this operation for different bare parts, the third
The arrangement shown in the figure is obtained (total wiring length sum = .゜゜25゛). Once this arrangement is reached, the arrangement will not be improved no matter what bears are replaced thereafter, so this becomes the final arrangement. Here, when selecting component bears, if all bear combinations are taken into consideration, the number of combinations becomes enormous, so adjacent components are often selected. However, even if
Even when combining adjacent component bears, in the placement process using the above method, the number of component replacement operations increases exponentially as the number of handled components increases, so the number of components is several 1.
The processing time becomes extremely long for numbers greater than 00, and the application of such a method is prohibited. Otherwise, even if it is applied, the current situation is that only extremely insufficient placement results can be obtained.Instead of performing the above placement processing using software using a general-purpose computer, the present invention performs most of the processing. The object is to provide a dedicated device for placement which reduces processing time by performing it in hardware.

The drawings will be explained in detail below. FIG. 4 shows an embodiment of the present invention, in which reference numerals 21 are memory units, 22
is an arithmetic unit, 23 is a data signal line, 24 is a control signal line, 25 is a multiphase clock generation circuit, 26, 27
, 28 and 29 are clock lines, respectively.

The memory unit 21 consists of a plurality of words and is connected to the arithmetic unit 22 via a data signal line 23 and a control signal line 24.

The arithmetic unit 22 has functions such as addition and subtraction, read/write control, and register functions. The multiphase clock generation circuit 25 generates four-phase clock signals and connects the clock lines 26,
A clock signal is supplied to the arithmetic unit 22 via 27, 28, and 29. The operation of this device will be explained in detail below with reference to FIG.

The operation of this device can be roughly divided into the following two phases. These are the initial arrangement set phase and the replacement and improvement phase. The explanation will be given below in order. (1) Initial arrangement set phase.

In this phase, the initial arrangement state is set in each memory unit 21 shown in FIG.

The information to be given to each memory unit is the number of the part assigned to that memory unit 21, the number and coordinate position of the single or plural parts to which that part is connected. In FIG. 4, signal lines and the like for writing this information into each memory unit 21 are not shown because they would complicate the drawing, but they are omitted because they can obviously be easily implemented using a known method. (2) Replacement improvement phase.

In this phase, starting from the placement given in the initial placement phase, each calculation unit 22 calculates whether the placement will be improved if the parts of the two memory b units 21 on the upper and lower sides or on the left and right adjacent to it are replaced. Depending on the results, the replacement may or may not be performed.

Which component bare is to be checked for replacement improvement is selected by supplying four-phase clock signals generated by the multiphase clock generation circuit 5 to each arithmetic unit 22. For example, when the clock line 26 becomes '6r5, Pl,2, P3,2,
P,,2,P7啼29P9ra2 and P1?69P39
69P5169P71691P9,6 has been selected, so the bare memory unit 21 (Ml, l,
Ml, 3), (M3, l, M3l3) 9 (M59l9M
593)9(M79l9M793)9(M99l9M9
,3) and (Ml,59Ml,7)9(M3,59M
3,7)9(M5◆59M597)9(M7ra59M7
97)9 (M9959M29,7) has been selected. Similarly, when the clock line 28 becomes ゜゛1゛, the memory unit 1 becomes bare (M3, l
,M5,l)9(M3,39M5,3)9(M3,5f
M5,5)9(M3,79M597)9(M99M5
Ya9) and (M79l9M9?1)92(M7,39
M9,3)9(M7,59M9,5)9(M7,79M
9, 7), (M7, 9, M9, 9) are selected. In this way, the clock lines 26, 27, 28, 2
If 9 becomes "゜1" at different times, all the bare memory units 21 will be selected and 3 will be selected.
It is determined whether or not there is an improvement in the placement of bare parts within the system by replacing them.If there is an improvement, the parts are replaced, and if not, they are not replaced.

The following explanation assumes that the clock line 26 is in the state of ゜"1". At this time, (Ml, l9Ml93
)9(M39l9M393)9,(M9ra59M997
), was selected as a bear, but among these, (
We focus on the bare Ml,l,Ml,3). memory unit Ml,l and Ml,3 by block calculation unit Pl,2.
Read the contents of Ml,, and calculate whether the total wiring length sum increases or decreases when assuming that the parts in Ml,, and the parts in Ml,3 are replaced, and if it decreases, read the contents of Ml,, and the parts in Ml,3. Replace numbers and associated information. If the information remains the same or increases, the information is not replaced. Such processing is performed for all the selected bears. As a result, when a component is replaced in one or more bare memory units, it is necessary to update the position information in the memory unit 21 in which components having a connection relationship with that component are stored. Therefore, the part number and position information are read from the replaced memory unit, and the contents of the memory unit in which the parts involved are stored are updated. To explain this using FIGS. 1 and 2 as examples, when parts 6 and 10 are exchanged, parts 5, 7, 9, 13, and 14 that are connected to part 10 also have parts 10. This corresponds to rewriting the position information from (X=1, Y=4) in FIG. 1 to (X=1, Y=3) in FIG. 2. In this way, when all changes in part position data caused by replacement are completed, the state will be the same as after the initial placement set phase (however, the part position will change from Figure 1 to Figure 2). ). Subsequently, as the clock line 27 becomes "r1" and the clock line 28 becomes "°1", different memory unit bears are selected one after another and the same process as above is repeated.

Repeat this operation to connect the clock lines 26, 27, 28, 29
The replacement phase is completed when there is no improvement due to replacement for any node bear after one cycle has passed, or when a certain amount of time has elapsed. The component position data stored in each memory unit at this point becomes the final arrangement. As explained above, the present device has the advantage of being able to solve the problem of placement determination, which was conventionally solved by software, directly in hardware, thereby making it possible to process the problem in an extremely short time.

Conventional software-based processing uses hardware called a general-purpose computer, but because it has a single arithmetic circuit, it can only process sequentially, but with the present invention, Parallel processing becomes possible with multiple arithmetic circuits. Therefore, a significant reduction in processing time can be expected compared to conventional software-based processing. In this embodiment, the memory unit array is 5×5, but this is generally N×m.

[Brief explanation of the drawing]

FIGS. 1, 2, and 3 are explanatory diagrams for explaining the placement improvement processing method, and FIG. 4 is a circuit diagram of an embodiment of the apparatus of the present invention. 21...Memory unit, 22...Arithmetic unit, 23...Data signal line, 24...
Control signal line, 25...multiphase clock generation circuit, 26, 27, 28, 29...clock line.

Claims (1)

[Scope of Claims] 1. Memory circuits arranged in an array, arithmetic circuits provided between each of these memory circuits having at least addition/subtraction, read/write control, and register functions, and rows and rows in which these arithmetic circuits are located. It consists of a circuit for supplying clock signals of different phases corresponding to columns, and each memory unit stores a part number and the numbers and positions of parts connected to that part as initial placement data, and Based on a predetermined evaluation standard, the arithmetic circuit determines whether or not the arrangement will be improved when parts stored in a pair of memory circuits adjacent to the arithmetic circuit selected by the signal are replaced. . A placement determining device characterized in that if an improvement is achieved, the parts are replaced, and if no improvements are made, the parts are not replaced. The arrangement is successively improved by repeating the process of replacing the parts, and obtaining a final arrangement. 2. Claim 1, wherein the arithmetic circuit is provided between adjacent memory circuits and is configured to access both of the adjacent memory circuits.
Placement determining device described in Section 1. 3. Claim 1, wherein each of the clock signals of different phases starts arithmetic processing in parallel in the plurality of arithmetic circuits to which the clock signals are applied.
The arrangement determining device according to item 1 or 2.