SU1153340A1 - Device for teaching how to write information in computer memory - Google Patents

Abstract

DEVICE FOR TEACHING RECORDING INFORMATION-IN MEMORY OF COMPUTER, containing address code generator, connected via the first and second address switches to the first and second drives of the drive, respectively, t-rety input of which is connected through the pulse shaper connected to the output of the number code generator. The first, second and third inputs of which are connected respectively to the output of the accumulator and the first and second outputs of the pulse distributor, the third output of which is connected to the input of the address code generator, characterized in that, in order to expand the didactic capabilities of the device, a pulse duration regulator is entered into it, the input of which is connected to the fourth output of the pulse distributor, the first output - to the second inputs. address switches, and the second output - with the second input of the pulse generator, and a series-connected generator of control codes and switch modes of operation, the output of which is connected to the fourth input of the driver of the number codes, the input of the generator of control codes is connected to the output of the driver of the address codes.

Description

The invention relates to teaching and laboratory equipment and is used to teach students to record information in a computer memory. The purpose of the invention is to expand the didactic capabilities of the device. Figure 1 shows the functional scheme of the device; figure 2 is a functional diagram of the pulse distributor; FIG. 3 is a pulse width regulator circuit. A device for training information recording in a computer memory contains an address code generator 1, connected via the first 2 and second 3 address switches, respectively, to the first and second inputs of the accumulator 4, the third input of which is connected to the output of the 6 number codes, the first input , the second and third inputs, which are connected respectively to the output of the accumulator 4 and the first and second outputs of the distributor 7 pulses, the third output of which is connected to the input of the driver 1 address codes, the controller 8 long pulses, the input of which is connected to the fourth output of the distributor 7 pulses, the first output to the second inputs of the address switches 2 and 3, and the second output to the second input of the generator 5 pulses, and a series-connected generator 9 control codes and the switch 10 modes work, the output of which is connected to a quarter of the input of a number codes, the input of the generator 9 control codes connected to the output of the address codes generator. Pulse distributor 7 (FIG. 2 contains synchronized pulse generator I1, cov and driver 12 of control signals of driver 1 address codes and driver of 6 number codes, the outputs of which are the outputs of pulse distributor 7 and connected to the inputs of driver address codes 59

and the number codes, respectively, the output of the generator II of synchronized pulses is the output of the block and is connected to the input of the regulator 8 of the duration of the pulses.

The pulse duration regulator 8 (FIG. 3 contains 3 pulse-codes connected in series, the output of which, through the switch 0, can be connected to the input of any of the digits of the generator of 6 number codes.

The control code is written to the accumulator 1 only in the control code mode, the driver 1 in this case provides natural-time signals and the driver 14 of variable duration signals, the outputs of which are the controller outputs and are connected respectively to the address switches 2 and 5 driver pulses The input of the pulse switch 13 is the controller input and is connected to the output of the pulse distributor 7. The device works as follows. The address code generator 1 controls the selection of the desired cell (core) of the drive 4, generates and stores an fi-bit address code consisting of two n / 2-bit groups (address code along the X and Y coordinates). Each of these groups controls the first and second address switches 2 and 3, respectively. The address switches provide the excitation of one address bus on the X coordinate and one address bus on the Y coordinate according to the address code, switching the direction of the currents in the address buses, depending on the Read mode. or Record. The numerical part of the device contains a shaper 6 number codes and a shaper 5 pulses. The t-bit number code from the imaging unit 6 number codes through the imaging unit 5 pulses is entered into the cell 4 of the accumulator 4 whose address is stored by the imaging unit 1 address codes. The pulse shaper 5 drives the discharge windings (prohibition windings) of the drive 4 and provides a current in them equal to. value, address half of the record. The shaper operates in the Record cycle and writes the current to the inhibit windings when O is necessary to be written to the corresponding cell of drive 4. Shaper 6 of the number code receives and stores the number code read from drive cores 4 and the amplified playback amplifiers (not shown). The shaper 1 of the address codes controls the generator 9 control enumeration of addresses. Synchronously with it, the 9 control code generator generates a numerical sequence (control code) —the alternation of zeros and ones, when writing them to the drive and then comparing them, an extreme, i.e. the heaviest mode of operation of accumulator 4, when the total uncompensated interference on the read wire approaches the maximum value. The pulse distributor 7 ensures the autonomous operation of the device and generates control signals of the required power, duration and with certain time intervals depending on the operating modes and commands, controls the address and numerical parts of the device. The proposed device is educational and has wide didactic possibilities. The pulse duration controller 8 makes it possible to control the pulse duration of the coordinate address currents that the address switches 2 and 3 send to the address buses X and Y of drive 4 in the Read cycle, as well as the duration of the time interval between two adjacent Read-Write pulses and down increases from nominal value. This makes it possible to demonstrate the temporal parameters of the memory device, such as speed, to determine the maximum speed that is permissible for a given storage device. The address switches 2 and 3 provide the ability to control and measure the current directly in the X and Y axis 4 of the drive in Read and Write cycles. This is necessary for characterization, for example, to determine the area of reliable information storage. The switch 10 modes, the operation provides, for example, in two modes - one-time "1 time" - five commands: Read, Write, Write control code, Clear drive, Clear GUcheck. a memory cell whose address is specified by the drivers of the I address codes. When executing the commands Record control code, Clearing the accumulator addresses are set automatically in ascending order. When the Cell Cleanup command is executed, the information in the cell whose address is specified by the driver of the I address codes is erased. All the characteristic points of the bit (numeric) and address channels are mapped to control sockets (not shown) and are available for observation using an indicator {), for example, an oscilloscope, of the processes occurring in the installation when reading or writing information in the drive. The outputs of the playback amplifiers, amplifying the signals in the winding of the readings of the accumulator 4 arrays, are also output to control sockets (not shown). The playback path in one of the bits is derived for control in more detail. In this bit there is an amplitude adjustment (signal at the amplifier output, here you can also observe the output gating process (to avoid interference based on the time selection principle. Inputs of the 6 number codes through the switch 10 operating modes are connected to the outputs of the 9 control code generator. Command The control code recording gives the opportunity to check the accumulator operation in the write, store and read mode of the hard code when the total uncompleted interference on the read wire approaches The raster scan unit makes it possible to observe the entire storage array on a oscilloscope screen at once (not shown). The control sockets of the pulse distributor 7 (not shown) make it possible to observe the main signals on the indicator, making up a cycle of accessing the memory device. These signals ensure the synchronous operation of all device nodes. The sequence of the cycle signals is framed with special auxiliary signals (for synchronization, for example, of an oscilloscope). One can observe how this sequence is applied depending on the command being executed.

R

} H & 1.6

. 2

at

I

ia 3

Claims (1)

DEVICE FOR LEARNING INFORMATION INFORMATION IN COMPUTER MEMORY, containing the address code generator, connected through the first and second address switches respectively to the first and * second inputs of the drive, the third input of which is connected via the pulse generator to the output of the number code generator, the first, second and third inputs which are connected respectively to the output of the drive and the first and second outputs of the pulse distributor, the third output of which is connected to the input of the generator of address codes, characterized in that, with the goal To expand the didactic capabilities of the device, a pulse duration controller is introduced into it, the input of which is connected to the fourth output of the pulse distributor, the first output to the second inputs. address switches, and the second output with the second input of the pulse shaper, and a series of control code generator and a mode switch, the output of which is connected to the fourth input of the number code shaper, the input of the control code generator is connected to the output of the address code shaper. Λζί. 1 SLL> ι> .1153340 1 1153340 2