SU1152042A1 - Storage with error correction - Google Patents

Abstract

STORAGE DEVICE WITH A CORRECT SHIBOK, containing a drive, a decoding unit, a correction unit, the first decoder, the first element OR, the second decoder, the first block of elements. And, a direct code register, a control unit, the first output of the decoding unit is connected to the inputs of the first OR element and the first decoder, the output of which is connected to one input of the correction unit, the output of which is connected to one input of the first AND block, and the second output of the decoding unit and the output of the first element .OR is connected to the inputs of the second decoder, one output of which is connected to the first and second inputs of the control unit, the third input of which is the control input of the device, characterized in that To increase the reliability of the device, the second block of AND elements, the inverter block, the second OR element, the first and second OR block, the inverse code register are entered into it, and the drive output is connected to one input of the second AND block and inverter block whose outputs are connected to the inputs of the first block of OR elements, the output of which is connected to the input of the decoding unit, another input of the correction unit and one input of the register of the inverse code, the output of which is connected to the drive input, the output of the correction unit is connected with one input of the forward L code register, the output of which and the output of the first C block of elements AND are connected to the inputs of the second block of elements OR whose output is the information output of the device, the other outputs of the second decoder are connected to the inputs of the second OR element whose output is connected to the fourth the input of the control unit, the first and sixth outputs of which are connected to other inputs of the inverse code register, the other inputs of the direct code register are connected to the third and sixth outputs of the control unit, the first, fourth and the seventh outputs of which are connected respectively to the other inputs of the second power supply unit I, the first power supply unit And, and the inverter power unit, the second and fifth outputs of the control unit are indicator outputs of the device.

Description

11 The invention relates to fifteen technology and can be used as the main and auxiliary storage devices in computing systems. Memory devices are known that contain a drive, an address register, coding and decoding blocks associated with a drive, input and output registers, one-to-one comparison block, blocks of AND and HW O and 2 elements. The disadvantages of these devices are redundancy, as well as incorrect correction when errors, the multiplicity of which exceeds the correction ability of the applied code. It is also known that a memory device with error correction contains a drive, the output of which is connected to the inputs of the forward and reverse code registers, a block for detection of failed bits, the inputs of which are connected to the direct outputs of the forward and reverse code registers, a correction device whose input is connected with the output of the direct code register, the equality scheme of the codes to which input the inputs of the block of detection of the failed bits and the correcting device are connected, the control unit whose inputs are connected with the outputs of the corrector Editin devices and circuits equality codes, and outputs to the inputs of registers forward and reverse codes and block elements and to whose second inputs connected to the output of the correction device. The output of the direct code register is connected to the input of drive Z. The closest to the invention is an error correction memory containing a drive whose output is connected to one input of a correction unit and an input of a decoding unit, one output of which is connected to the inputs of the first decoder and first element OR, the output of which and another output of the decoding unit are connected to the inputs of the second decoder, the outputs of which are connected to the control unit, the output of the first decoder to another input of the correction unit, output which is connected to one input of the element I, the other input of which is connected to the output of the control unit, the first inputs of the other elements AND, respectively, to the input of the accumulator and the output 22 of the decoding unit, the second inputs to the outputs of the control unit, the outputs of the other elements to the inputs of the direct register code c. A disadvantage of the known devices is the limited correction capacity for the occurrence of errors caused by failures, as well as the combined effect of failures and failures. The aim of the invention is to increase the reliability of the device. The goal is achieved in that an error-correcting memory device containing a drive, a decoding unit, a correction unit, a first decoder, a first OR element, a second decoder, a first AND block, a direct code register, a control unit, and the first output of a decoding unit connected to the inputs of the first OR element and the first decoder, the output of which is connected to one input of the correction unit, the output of which is connected to one input of the first block of elements And, the second output of the decoding unit and the output of The second OR element is connected to the inputs of the second decoder, one outputs of which are connected to the first and second inputs of the control unit, the third input of which is the control input of the device, the second block of AND elements, the inverter block, the second OR element, the first and second blocks of the OR elements, are entered the register of the inverse code, the drive output being connected to one input of the second block of elements AND and the inverter block, whose outputs are connected to the inputs of the first block of OR elements whose output is connected to the input of the decoding block, Another input of the correction unit and one input of the inverse code register, the output of which is connected to the accumulator input, the output of the correction unit is connected to one input of the direct code register, whose code and output of the first block of AND elements are connected to the inputs of the second block of OR elements, whose output is the information output of the device, the other outputs of the second decoder are connected to the inputs of the second OR element, the output of which is connected to the fourth input of the control unit, the first and sixth outputs of which are connected to each other and register inverse (LH) cal, the other inputs of the direct code register are connected to the third and sixth outputs of the control unit, the first fourth and seventh outputs of which are connected respectively to the other inputs of the second block of elements And, the first block of elements And and the inverter unit, the second and n These outputs of the control unit are indicator outputs of the device. FIG. 1 shows a block diagram of the device; in fig. 2 is a control block diagram; Fig. 3 is one of the variants of the decoding block. The device contains a drive 1 whose code is connected to the first inputs of the second block 2 elements AND and the block 3 inverters, the outputs of blocks 2 and 3 are connected by the inputs of the first block 4 elements OR, the output of which is connected to the input of block 5 decoding by one input, block 6 correction and register 7 of the inverse code, the output of which is connected to the input to the drive 1. The output of the correction unit 6 is connected to one input of the first block 8 elements AND and the register 9 direct code, the outputs of which through the second block 10 elements OR are connected to the trunk 1t . Information outputs 12 of block 5 are connected to the inputs of the first element OR 13 and the first decoder 14, the output of which is connected to another input of the correction unit 6. The output of the first element OR 13 is connected to the first input of the second decoder 15, the control output 16 of unit 5 is connected to the second. The first and second outputs of block 15 are connected to the inputs of the second element OR 17, the output 18 of which is connected to one of the inputs of control unit 19. The third output 20 and the fourth output 21 of the unit 15 are connected to the inputs of the unit 19. The input 22 of the unit 1.9 receives the signal Read from the central control unit. The output 23 of the control unit 19 is connected to the first control to the whole input of the unit 7 and to the control input of the unit 2, the output Error 24 of the unit 19 of the signal 19 appears, the outputs 25 and 26 of the control unit 19 are connected respectively to the first control input of the unit 9 and control The read input of block 8 and control block 19 of control 24 is connected to the second input of block 7 and 9 and the control input of block 3. Control block 19 (Fig. 2) contains two-input elements And 30 and 31, the first inputs of which They are connected to the output 20 of the second decoder 15, elements And 32 and 33, the first inputs of which are connected to the output 21 of the second. the decoder 15, the first trigger 34, whose input is connected with the output of the element And 30, the second trigger 35, the input of which is connected with the output of the element And 32, the element OR 36, to the inputs of which are connected the outputs of the elements 30 and 32. The input 22 is connected to the delay element 37, the output of which is connected to the second inputs of the AND elements 30 and 32. The output of the element: OR 36 is connected to the input of the delay element 38, whose output 29 through the delay element 39 is connected to the second inputs of the AND elements 31 and 33. To the first input of the AND element 40, trigger output 34 is connected, to the second, output element I 31. The first input of the element 41 is connected to the output of the trigger 35, the second to the output of the element 31. The first input of the element 42 is connected to the output of the trigger 35, the second to the output of the element 33, the first input of the element 42 to the output of the trigger 34, the second - with the output of the element And 33. The inputs of the three-input element OR 44 are connected to the output of the element And 42, the output of the element And 43 and the output 18 of the element OR 17. The output of the element And 41 is connected to the first input of the element OR, and to the second - the output of the element OR 44. FIG. 3 shows one of the possible options for constructing a block of 5 decoding with m 8 bits (g is the length of words, store "1x in drive 1). Block 5 consists of two-input modulators 45 and 46 modulo two, the inputs of which are connected to the corresponding bits of the word from the output of block 4, satisfying the rule of forming the check bits for the Hamming code correcting one and detecting two errors. Correction block 6 should be performed on two-input modulators two (elements EXCEPT OR), the first inputs of which are connected to the outputs of block 4, and the second - the outputs of the first decoder 14. information stored in the Hamming code correcting one and detecting two mistakes. Such a code has the main check bits (OCD), each of which controls its parity of groups of parities (the groups are formed so that the OCR polling indicates the location of the error), and one additional control section (DCR) that performs the parity of the entire word . The decoding unit 5 determines the OCD value coming from the output 12 to the OR element 1., and the DKR value at the output 16. The signals from the output of the OR element 13 and the output 16 of the decoding unit 5 arrive at 15. The decoding result and operation of the decoder 15 are described table. If DKR is O, OCD is O, then this means that the decoded word contains no errors. The combination of DKR 1 OCR O indicates the presence of a one-time error in the additional (zero) test bit of a word or an error of odd multiplicity (3.5 .. tatsoy that the sum of the numbers of erroneous bits modulo two is zero. More likely the first case, therefore , output 18 of the element OR 17 receives a control signal O, as a signal of the absence of errors in the word. In the sentence SO

In the case of a combination of DCR 1 and OCD O, the value of the additional control bit is not corrected, since it is assumed that it will not participate in further operations. If it is necessary to use it, then the second output of the block 15j is also necessary to be provided in the trigger 34.

Both in the first and in the second case, from the output 28 of the IZH 36 element, a signal is issued, according to which the contents of register 7 from its inverse output are recorded in the same cell of the accumulator, according to a signal from the 28 code, the information from block 6 KoppeKij iH must be turned to zero block 6 correction. With DKR O and OCD 1 at the output 20 of the decoder 15, the control signal 2 is shown in accordance with the Wits, indicating that the word contains an uncorrected but detectable error of even multiplicity (2,4,6 ...). The value of DCR 1 and OCD 1 means that there is an odd multiplicity error (1.3 ...) in the word, and output 21 of the decoder 15 turns on the control signal 1. The read operation is initiated by the Read signal received at input 22 of block 19 management The information from the output of accumulator 1, by the signal from output 23 of block 19, passes through blocks 2 and 4, enters block 5 of decoding and block 6, and by signal from output 23 of block 19 is written to register 7. The values of basic check bits calculated in block 5 decoding from output 12, goes to the decoder 14, which, in accordance with the received code, inverts one of the word bits (1 - n) in correction block 6, if from output 12 a non-zero code arrives. In the absence of errors or in the presence of a one-time error, a signal O arrives at the third input of the OR element 44 of the control unit 19, at the output 18 of the element OR 17, the signal to the block of the 8 elements AND is resolved; The passage of information from the correction block 6 through the block 10 elements OR to the numerical line 1 1. From the output 27 of the element OR 45 of the block 19, the Ready signal is set. When appearing at the output 21 of the decoder 15 of the control signal 1, an element 32 is triggered, the second input of which at this time receives a signal from the output of the delay element 37, and the signal 1 is stored in the trigger 35. In a similar way, the control signal 2, if such a decoding outcome is stored in register 9 of the direct code, and, in addition, it is fed to the input of delay element 38. Then it re-reads the information. The signal from the output 29 of the delay element 38 allows the information to pass through the block 3 inverters. The newly read word through block 4 is fed to the inputs of blocks 5 and 6. In blocks 5,6,13 t4,15 and 17, the same actions are performed as at the first reading. If the read word does not contain errors, then the output signal 26 elements OR 44 of block 19 permits the passage of information from correction block 6 through the first block of 8 elements AND, bl of 10 HJHi elements into the numerical highway 11, and output 27 of the WL 45 unit of block 19 enters the Signalization signal indicating a reading operation. If the output signal 20 of the decoder 15 is tuned to the control signal 2, then the element 31, the second input of which at this moment receives the signal from the output of the delay element 39, will operate. If in the first reading cycle, the outcome of the decoding was signal 2, stored in trigger 34, which triggered element 40, and error signal was output at output 24, but if in the first cycle the result of decoding was signal 1, then element 41 would work, 25 which information from register 9 through the second block 10 elements OR enters numerical line 11, and from output 27 Ida45 element receives a ready signal. When signal 1 appears at output 21 of deashfrathra 15, element 33 is triggered and either element 42 of block 19 or element and 43 (depending on the outcome of coding in the first reading cycle), and the signal from output 26 of the element OR 44 information from the output of block 6 through the first block 8 of the elements AND, the second block 10 of the elements OR enters the numerical highway 11, while the output 27 of the element OR 45 appears Signal Ready. Example. Let initially be written into some cell of accumulator 1 information looked like 01011010, 42 Hell - an additional check bit; main test bits. Each of the check bits controls by parity its group of bits (these bits are underlined). Let, when addressing a given cell, at the output of a block of elements OR 4, a word containing two errors is received. Suppose that in the 5th bit, the error was caused by a failure, and in the 6th bit, the error was caused by a failure. The read word is written to register 7, enters blocks 5 and 6. The first control ratio does not hold (at output 12.1 of the adder 52 modulo two (Fig. 3) of block 5, the signal is one), the second control ratio does not hold (on output 12.2 of adder 53, the signal is equal to one), the third control ratio is satisfied (at output 12.3, the signal is zero), i.e. The decoder 14 receives the code 011, and in the correction block 6, the third digit of the read word is inverted. The additional control ratio is satisfied (the signal at the output 16 of the adder 56 is equal to zero), at the output of the element OR 17 the signal is equal to one, i.e. The decoder 15 receives the code 01 (see table). At the output 20 of the decoder 15, the control signal 2 appears, the element And 30 of the block 19 is triggered, and the trigger 34 is set to one. A single signal appears at the output of the OR 36 element, according to which the control signals are outputted from output 28, the contents of register 7 from the inverse output are written to the same cell of accumulator 1 and look like 10100011, and information from block 6 is entered into register 9. Then the word is re-read. The signal from the output 29 of the lock 19 allows the passage of information through the block 3 inverters. The read information has the form 10100 | 1 1, and after passing through block 3-01011000. This information comes in blocks 5

. 9 i1

and 6. At outputs 12.3-12.1 of block 5, code 110 appears, which goes to decoder 14, in block 6 the sixth bit of the word is inverted. The signal at output 16 of block 5 is equal to one, the code 11 goes to the input of the decoder 15- and outputs control signal 1 from output 21. And block 33 triggers, block 19, element 43, and control pin 26 comes from output 26 of element OR 44 and the contents of block 6-0101 101 through blocks 8 and 10 enters the numerical line 11. From the output 27 of the element OR 45 of block 19, the signal Readiness comes, I testify

210

about the end of the read operation.

Error multiplicity two fixed.

The proposed device allows the correction of errors caused by failures, failures and their joint action. If errors are caused only by failures, then the device corrects 1-, 2-nd 3-fold errors. If errors are caused only by failures, then the device corrects only one fold error and detects a double error. When sharing

In the case of failures and malfunctions, the device always corrects a double error (one error caused by failure, one failure).

(1 I

i

FIG. g

Claims (1)

A MEMORY CORRECTING DEVICE, comprising a drive, a decoding unit, a correction unit, a first decoder, a first OR element, a second decoder, a first AND block, a direct code register, a control unit, the first output of the decoding unit being connected to the inputs of the first OR element and the first a decoder whose output is connected to one input of the correction unit, the output of which is connected to one input of the first block of AND elements, the second output of the decoding unit and the output of the first element. OR connected to the inputs of the second an encoder, one of whose outputs is connected to the first and second inputs of the control unit, the third input of which is the control input of the device, characterized in that, in order to increase the reliability of the device, a second block of AND elements, a block of inverters, a second OR element, the first and the second block of OR elements, an inverse code register, and the drive output is connected to one of the inputs of the second block of AND elements and the inverter block, the outputs of which are connected to the inputs of the first block of OR elements, the output of which is connected to the input the decoding unit, the other input of the correction unit and one input of the inverse code register, the output of which is connected to the drive input, the output of the correction unit is connected to one input of the direct code register, the output of which and the output of the first block of AND elements are connected to the inputs of the second block of OR elements, the output of which is the information output of the device, the other outputs of the second decoder are connected to the inputs of the second OR element, the output of which is connected to the fourth input of the control unit, the first and sixth outputs of which are connected are with other inputs of the inverse code register ^{:: the} other inputs of the direct code register are connected to the third and sixth outputs of the control unit, the first, fourth and seventh outputs of which are connected respectively to other inputs of the second block of elements AND, the first block of elements AND and the block of inverters, the second and fifth outputs of the control unit are indicator outputs of the device. > 1 1 5204 2