SU1128385A1 - Converter of delta modulated signal to signal with pulse-code modulation - Google Patents

Abstract

CONVERTER DELTAMODULIROVANNOGO signal to a signal with pulse code modulation comprising a down counter, a first D-trigger, the R-input of which is connected to an output significant bit down counter, a input sinhronizatsiis synchronization bus, the counter and the first logic unit of m n and h a y and u with the fact that, in order to improve noise immunity, s, the second logic block, the EXCLUSIVE OR-NOT element and the second D-trigger, whose synchronization input input is connected to the synchronization bus, are input reverse synchronization about the counter and the input of the counter, the output of the second is connected to the first input of the second logic unit, and the input of the installation to the counter - to the output of the EXCLUSIVE YLI-NE element, the first input of which is connected to the output of the first D-trigger, and the second input is connected to the D input of the first D -trigger and the first input of the first logic block, the second input of which is connected to the second input of the second lo (Logical block and the output of the second D-flip-flop, the third input of the first logic block is connected to the input of the device and the control input of the reversive counter, a output - with the input of the prohibition of the counting of the reversible counter and the third input of the second logic block, the output of which is connected to the D-input of the second D-flip-flop;

Description

I The invention relates to a pulse technique and can be used in digital signal processing and transmission systems in which delta modulation (DM) and impedance-code modulation (PCM) are used. : A device is known for converting DM.algunts to PCM containing adders, resistors, multipliers, and permanent memory devices. The disadvantage of this device is low. Noise resistance The closest technical solution to the invention is to install. A device for converting delta-modulated signals into a PCM signal containing a reversible counter, a D-flip-flop, the D input of which is connected to the higher-order output of the reversing counter, and a synchronization input to the synchronization bus, controlled by a frequency divider, for example, a counter and the first logical the unit as well as the high-frequency delta-modulator, the direct and inverse outputs of which through the elements AND are connected to the control input of the reversible counter, and the 2J clock generators The disadvantage of the known device is low immunity, which causes a change in the level of the D.C. in the output PCM signal in the event of failures in the DM signal and leads to distortion of the transmitted signals. This is due to the fact that reversible counters are with ideal integrators, as a result of which they accumulate errors. The purpose of the invention is to increase noise immunity. The goal is achieved by converting a delta-modulated signal into a pulse-modulated signal containing a reversible counter, the first B-flip-flop, the D input of which is connected to the high-end output of the reversible counter, and the synchronization input is connected to the synchronization bus, the counter and the first logic block, the second logic block, the EXCLUSIVE OR NONE element and the second D-trigger, whose synchronization input is connected to the synchronization bus, the synchronization input of the reversible counter, and the input of the counter, whose output is connected Inen with the first input of the second logical block. and the installation input in About counter - with 852 output element EXCLUSIVE OR NOT, the first input of which is connected to the output of the first D-flip-flop, and the second input is connected to the D-input of the first D-flip-flop and the first input of the first logic unit, the second input of which is connected to the second the input of the second logic block and the output of the second D-flip-flop, the third input of the first block is connected to the device input and the control input of the reversible counter, and the output is connected to the prohibition input of the reversible counter and the third input of the second logic block whose output Single with D-input of the second trigger. The drawing shows the functional diagram of the device. The device contains a reversible counter 1, the control input of which is connected to the input 2 of the device, the synchronization input is connected to the synchronization bus 3, the outputs of the reversible counter 1 are the output 4 of the device, the counter 5, the first and second triggers 6 and 7, the element 8 EXCLUSIVE OR NOT the first and second logic blocks 9 and 10, the synchronization bus 3 being connected to the input of the counter 5 and the synchronizing inputs of the first and second D-flip-flops 6 and 7, and the output of the high bit of the reversing counter 1 is connected to the first input of the first logic unit. 9, to the first input of the element 8 EXCLUSIVE OR NOT and to the input of the first D-flip-flop 6, the output of which is connected to the second input of the element 8 EXCLUSIVE IL-NOT, the output of which is connected to the input of the installation in O of the counter 5, and the output of the counter 5 to the first the input of the second logical unit 10, the extrinsic of which is connected to the D-input of the second Dtrigger 7, the output of which is connected to the second inputs of the first and second logical blocks 9 and 10, the third input of the first logical unit 9 is connected to the input 2 of the device, and the output to the inhibit input reversible counter 1 and third input accounts One second logical unit 10. Counter 5, D-flip-flops 6 and-7, element 8 EXCLUSIVE OR NOT, blocks 9 and 10 form a block 11 for automatically decreasing the level of the constant component in the decoded PCM signal. The device works in the following way.

The input signal in the form of the DM sequence is fed to the control input of the reversible counter 1, which is also the input 2 of the device. The reversible counter 1 can be any reversible counter Bm, which has a direction control-billing control input, a count inhibit control input and a sync input on which synchronization buses 3 receive sync pulses, the PCM output code is removed from the outputs of the reversing counter 1, which are output 4 of the device.

The control input of the prohibition of the account of the revisive counter 1 is connected to you-. the course of block 11 of automatically decreasing the level of the constant component in the output PCM signal. The operation of block 11 is based on the determination of whether. Does the sign (most significant bit of the reversing counter 1) of the output PCM signal change in silence mode for the period T / (, where c is the lowest frequency of the transmitted signal. The period T is determined by the counting factor of the counter 5, which divides the clock frequency. Counter 5 may be a counter of any type of desired width with a decryption output of the fill state and an installation input into the O. I

Depending on the sign of the PCM signal at the end of the period T and on the level of the input DM signal by the unit 11 for automatically decreasing the level of the constant component, an additional signal is generated that controls the operation of the reversible counter 1. such that in the case of the higher discharge counter of the reversible counter changes its value over a period T, the state of the reversible counter 1 changes by a unit of the least significant bit in the direction of decreasing the constant component. The PCM signal is fixed in two adjacent synchronization cycles, performed by the firstB-trigger 6, the signal from the output of counter 5, which means that the period T has passed, is accomplished by the second D-trigger 7. Both D-triggers are synchronous D-triggers to the inputs synchronization pulses from the sync 3 bus. If during the period T the sign of the PCM signal changes, then element 8 EXCLUSIVE OR OR - NB produces a signal that resets to 0. counter 5, In this case, the second D trigger 7 does not fix the signal indicating that the period T has expired. additionally controlling the operation of the reversible counter 1 at the input of the prohibition of the account, is produced by the first logic unit 9. This combinational device, which, depending on the element base chosen, can be implemented on various logical elements in accordance with the table test of the truth of his work (Table 1), where Y is the output signal of the first logic block 9, the Signal is Allowed coded with zero, and the Unity of Count Cause is encoded with zero XI is the signal at the output of the high bit of the reversible counter 1; X2 signal at the output of the second) trigger 7; HZ - DM input signal,

Table 1

The second logic unit 10 is required to write to the second) -trigger 7 signal from the output of counter 5 and set this trigger to the initial state after the function of additional control of the reversible counter 1 is implemented. The second unit 10 is also a combinational circuit, the implementation which can be carried out on the basis of the truth table (Table 2), where Y is the output signal of the second logical block 10; XI - signal from the output of the counter 5; X2 is the signal from the output of the second) trigger 7; HZ - sigial from the output of the first logical block 9.

Table 2,

About About 1 1 About

About 1 About 1 About

Oh oh

about about 1

continuation of table 2

about 1 1

one

O 1 o

About 1

Thus, the introduction of an additional logic block, a second) trigger, and an EXCLUSIVE OR NOT element allows the converter to transmit the CM signal to the PCM signal with an integrator leakage, which increases the noise immunity of the converter to faults in the delta-modulated signal.

Claims (1)

A DELTAMODULATED SIGNAL CONVERTER TO A SIGNAL WITH A PULSE-CODE MODULATION, containing a reverse counter, the first D-trigger, the D-input of which is connected to the high-order output of the reverse counter, and the synchronization input with the synchronization bus, the counter and the first logic block, The reason is that, in order to increase the noise immunity, a second logical block, an EXCLUSIVE OR-HE element and a second D-trigger, the synchronization input of which is connected to the synchronization bus, the synchronization input of the reverse counter, are introduced into it and counter input, the output of which is connected to the first input of the second logical unit, and the installation input to O ”of the counter is connected to the output of the EXCLUSIVE YES or NOT element, the first input of which is connected to the output of the first D-trigger, and the second input is connected to the D-input of the first D-trigger and the first input of the first logical block, the second input of which is connected to the second input of the second logical block and the output of the second D-trigger, the third input of the first logical block is connected to the input of the device and the control input of the reversible counter, and the output is connected to the input ETA account down counter and a third input of the second logic block, the output of which is connected to the D-input of the second D-flip-flop. 5SUSZn ^m 'nS' ^eo 1 1128385 2