SU1124280A1 - Interface for linking computer with communication channels - Google Patents

Abstract

A DEVICE FOR COUPLING A COMPUTER WITH COMMUNICATION CHANNELS, containing the first input channel switch, the tuning register, the first number register, the clock counter, the pause counter, the comparison unit, the information input of the tuning register being the master input of the device, the output of the tuning register connected to the input input of the first input channel switch, the output of which is connected to the information system of the first register of the number, the input of the permission to issue information of which is connected to the control input of the comparison unit and to the output the house of the clock counter, the counting input input of which is connected to the resolution input input of the first register number and the output of the pause counter, the counting input of which is connected to the counting input of the NS clock counter, the synchronous input of the first number register, characterized in that, in order to increase the reliability of operation, The device entered a group of matching elements, the second input switch channels. an output switch, four consecutive adders, two accumulating adders, a second number register, three OR elements, and the inputs of the group matching elements form the information input of the device, and the output of the output switch is the information output of the device, the first input of the first SS element is a clocking input devices, the outputs of the group matching elements form the information inputs of the first and second input switches of the channels, the sampling input of the second input switch of the channels It is connected to the output of the setup register, the output of the first input (the channel switch is connected to the first input of the second OR element, the second input of which is connected to the inverter output of the first input channel switch and to the information input of the second number register whose output is connected to the first information output inputs of the commutator 4, the first and second successive adders, respectively, the second 00 information inputs of which are connected to the output of the first register of the number, the output of the second input switch The channel channel is connected to the first input of the third SHS element and to the information input of the first accumulator adder, the output of which is connected to the first information inputs of the third and fourth successive adders, respectively, the second information inputs of which are connected to the output of the second accumulating adder, information input

Description

which is connected to the inverse output of the second input switch of channels and to the second input of the third OR element, the output of which and the output of the second OR element are connected respectively to the second and third inputs of the first EH element, the output of which is connected to the synchronous inputs of the first and second registers of the first and second numbers nag of the accumulating adder, the first, second, third and fourth successive cyfMatopos, the resolution inputs for issuing the second register of the number, the first and the second wooded adders, respectively, are connected to The output of the sync-yuls counter, the input gates of the reception of the register of the number, the first and second accumulating adders, respectively, are connected to the output of the pause counter, the output of the first sequential adder is connected to the first information input of the comparator unit, the second information input of which is connected to the output of the third consecutive adder, the third information input the comparison unit is connected to the output of the third series adder and to the third information input of the output switch, the fourth The first information input of which is connected to the outputs of the fourth consecutive adder and to the fourth information input of the comparison unit, the output of which is connected to the control input of the output switch. )

The invention relates to computing and can be used as a receiver of the sequential code of computer systems for collecting and processing information.

Known digital transmission system, serial codes over a two-wire line with speed, defined. made by synchronizing pulses fl.

However, this device transmits information from one subscriber and cannot serve a group of subscribers at the entrance.

The closest to the proposed technical essence and the achieved positive effect is a device for interfacing a computer with communication channels, containing a channel switch, connecting to a device of a selected channel, whose information inputs are connected to communication channels, the information output is connected to an information input register of the number recording, storing and transmitting information to a digital computer, and the switch's synchronizing output is connected to the first input of a single pulse generator (GOI), which generates working pulses on the front of the received pulses, and from the control to the input of the pause counter,

intended to determine the beginning of the current word. The output of the pause counter is connected to the second control input of the number register and the control input of the clock counter (SI) to determine the completeness of the received code, the count input of which is connected to the GOI output and the clock register input of the number, and the output

connected to the installation input of the SI counter, which prohibits the input of the register

the number and the enable input of the comparison unit, designed to compare the first four bits of the word in the register of the number and array number from the setup register, intended to control the channel switch, set the number of received

words and array numbers of the received information, the first information input of the comparison unit is connected to the output of the number register, the second information input — to the output of the register

and control input of the switches.

The known device works as follows.

The communication channel selected by the configuration register is connected to the number register by the switch. The pause counter determines the beginning of the word of information, and the SI counter determines the completeness of the received information. The information1D1 from the output of the register is fed to the input of the comparison circuit, where the first four bits of the received word-word array are compared, stored in the tuning register. In case of coincidence, the information passes. To the input of the digital computer, defined by The number of received words is subtracted by one and the cycle repeats t2. The advantage of the prototype in comparison with the analog is that it allows working with several sources of information of the sequential code. The disadvantage of the prototype is low reliability, due to the fact that it does not provide an increase in the reliability of information when errors occur as a result of failure of individual elements of the device. The aim of the invention is to increase the reliability of work. The goal is achieved in that the device for interfacing a computer with communication channels, comprising a first input channel switch, a setup register, a first number register, a clock counter, a pause counter, a comparison unit, the information input of the setup register being a device input, the output of the setup register is connected to the sample input of the first input switch; the channel, the output of which is connected to the information input of the first number register, the input of which the information is issued, is connected to the control The input of the comparator and with the output of the clock counter, the input of the account resolution of which is connected to the input of the information reception of the first register of the number and the output of the pause counter, the counting input of which is connected to the counter input of the counter of clock pulses and the sync input of the first register of the number, are entered the group of matching elements , the second input channel switch, the output switch, four successive adders, two accumulators, the second register of the number, three OR elements, and the inputs of the The group's laps form the information input of the device, and the output of the output switch is 804 information output of the device, the first input of the first element OR is the clock input of the device, the outputs of the group matching elements form the information inputs of the first and second input channel switches, the sample input of the second input switch is connected to the output of the setup register the output of the first input switch of the channels is connected to the first input of the second OR element, the second input of which is connected with the inverse output of the first input channel switch, and with the information input of the second number register, the output of which is connected to the first information inputs 1 of the output switch, the first and second successive adders, respectively, the second information inputs of which are connected to the output of the first number register, the forward output of the second input the channel switch is connected to the first input of the third OR element and to the information input of the first accumulating adder, the output of which is connected to the first information iG: on-line inputs of the third and fourth successive adders, respectively, the second information inputs of which are connected to the output of the second accumulator of the adder, whose information input is connected to the inverse output of the second input channel switch and to the second input of the third OR element, whose output and output of the second OR element are connected respectively with the second and third inputs of the first element OR, the output of which is connected to. the sync inputs of the first and second registers of the number, the first and second accumulating adders, the first, second, third and fourth successive adders, the enable inputs for issuing the second register of the 1st number, the first and the second accumulating adders, respectively, are connected to the output of the clock counter, the receive enable inputs of the second number register, the first and second accumulating adders, respectively, are connected to the output of the counter; pause, the output of the first sequential adder is connected to the first information input of the comparison unit, the second information input of which is connected to the output of the second 5. sequential adder, the third information input of the comparison unit is connected to the output of the third successive adder and the third information input of the output switch, the fourth information input which is connected to the output of the fourth consecutive adder and with the fourth information input of the comparator unit, the output of which n with the control input of the output switch. The drawing shows the block diagram of the device. The device contains bus 1 connection with channels, first and second switches 2.3 channels, register 4 settings, group of matching elements 5, third element OR 6, first 7 accumulating adder, third 8 and fourth 9 consecutive adders, second 10 accumulating adder , comparison unit 11, output switch 12, bus 13 at the input of a computer, first 14 and second 15 elements OR, second 16 reg: tp numbers, first 17 and second 18 successive adders, first 19 number register, 20 pauses counter, 21 sync pulses. The device works as follows. Signals in the form of bipolar pulses on communication buses 1 are fed to the information inputs of switches 2, channels. The signals from register 4 settings go to the control inputs of the switches 2.3 and determine the number of the channel connected to the device. On the OR elements 6,15,14, the CKHxpontfaynbcos (SI) is extracted from the information by the Logic Table of the direct and inverse signal coming from the commutators 2.3, and during the transmission O or 1 at one of the outputs of the commutators 2.3 will be,. always positive momentum. Element 14 OR also receives clock pulses from a computer dp syncronization of the operation of a computer and device. When issuing information to the computer, the SI is fed to the input of the counter 21 of the SI and the input of the counter 20 pauses The counter 20 of the pause is zeroed by the SI. In the pause between the SI words, there are no bins, the counter 20 counts the reference frequency pulses, and if there is a specified distance of 0 pause, the counter code reaches the value corresponding to the gap between the words in the line and gives the enable signal to receive the serial end and the work permit counter 21 SI, To the input register 4 settings from the computer receives the control word (for example, 16-bit), Register 4 settings stores the number of the connected channel. The received information word is divided into two half-words A and B. With the arrival of the enabling pulse from the pause counter 20, writing to the first register on the 19th of the first half-word A begins, while the SI counter 21 counts the received word bits, and writes the second to the second 16 register. half word B. At the same time, in the first accumulating adder 7, the half sum B is located; in the second accumulating adder 10 there is a half-difference Γ - η. The recording and summation control in the accumulating adders produces counter 21 SI. After the arrival of the last digit of the word, the counter 21 prohibits the recording of information and gives permission for the output of information from the exchange device to the computer. The information is converted on successive 8,9,17 and 18, then the following operations are performed: on nepBiOM adder 17 there is a half-sum B -, on the second adder 18 there is a half-difference, (A - & I y, on the third adder 8 the sum A B + G and on the fourth adder 9. The difference between B C and G. These one radios are produced in bits, starting with the least significant bit. Information from the outputs of successive adders 8,9,17 and 18, registers 16,19 and accumulating adders 7 , 10 enters the comparison block 11, where B, C (±) occurs in operation A D G. Consider an example of Different combinations of results in block 11 are compared.

Claims (1)

DEVICE FOR COMMUNICATING A COMPUTER WITH COMMUNICATION CHANNELS, comprising a first input switch of channels, a setup register, a first number register, a clock counter, a pause counter, a comparison unit, wherein the information of the setup register is a setting input of the device, the output of the setup register is connected to a sample input of the first input switch channels, the output of which is connected to the information input of the first register of the number, the input of which permits the issuance of information of which is connected to the control input of the comparison unit and with the output of the count clock counter ·, the input of the resolution of the account of which is connected to the input of the permission to receive information of the first register and the output of the pause counter, the counter input of which is connected to the counting input of the counter of clock pulses, the sync input of the first register of the number, characterized in that, in order to increase the reliability of operation, the device introduced a group of matching elements, a second input channel switch, an output switch, four sequential adders, two accumulative adders, a second number register, three AND elements And, the inputs of the group matching elements form the information input of the device, and the output of the output switch is the information output of the device, the first input of the first OR element is the clock input of the device, the outputs of the group matching elements form the information inputs of the first and second input channel switches, and the sample input of the second input switch channel is connected to the output of the setup register, the output of the first input switch channel is connected to the first input of the second OR element, the second the input of which is connected to the inverse output of the first input switch of channels and to the information input of the second register of the number, the output of which is connected to the first information inputs of the output switch, of the first and second sequential adders, respectively, the second information inputs of which are connected to the output of the first register of the number, the output of the second input switch channels is connected to the first input of the third OR element and to the information input of the first accumulating adder, the output of which is connected from the first and data inputs Fi □ About the third and fourth sequential adders, respectively, whose second information inputs are connected to the output of the second accumulating adder, the information input of which is connected to the inverse output of the second input switch of channels and to the second input of the third OR element, the output of which and the output of the second OR element are connected, respectively with the second and third inputs of the first OR element, the output of which is connected to the clock inputs of the first and second registers of the number, the first and second accumulating adders in, the first, second, third and fourth consecutive adders, the enable inputs for the second register of the number, the first and second accumulating adders are respectively connected to the output of the clock counter, the enable inputs of the second register of the number, the first and second accumulating adders are respectively removed from the output of the pause counter , the output of the first sequential adder is connected to the first information input of the comparison unit, the second information input of which is connected to the output of the second In the output adder, the third information input of the comparison unit is connected to the output of the third serial adder and to the third information input of the output switch, the fourth information input of which is connected to the output of the fourth serial adder and to the fourth information input of the comparison unit, the output of which is connected to the control input of the output switch.