SU1104515A1 - Firmware control device - Google Patents

Abstract

1. FIRMWARE CONTROL MICROPROGRAMME, containing the block of elements AND, the element NOT, two elements TA, two RS-flip-flops, a counter, an address register, a memory block, a micro-command register, a control unit, an micro-co-operation unit and an output which is connected to the information input of the address register, the input of the initial setting of the address register is the first input of the device, the output of the memory block is connected to the input of the register of microcommands, the first output of which is connected to the information input of the control with the first information input of the micropetet formation unit, the first output of the microoperations forming unit is the first output of the device, the second output of the micro-command register t is connected with the second information input of the control unit and with the first information input of the micro-address address generation unit, the second information input of which is the second input of the device the stop input of the micro-command address generation unit is connected to the zero output of the first trigger, the zero output of the second trigger is connected to the first input p And, the outputs of the counter are connected to the inputs of the second element AND, characterized in that, in order to increase the reliability of the operation, a comparison block, a synchronization block, three delay elements, five OR elements, two blocks of AND elements and a block of OR elements are entered into the device i. moreover, the output of the address register is connected to the first inputs of the first and second (LI blocks of elements AND, the codes of which are connected to the information input of the counter and the first input of the block of elements OR, respectively, the output of the counter is connected to the first information input of the comparison block and the first input of the third block of elements And, the output of which is connected to the second input of the OR block, the output of the block of the OR elements is connected to the second information input of the comparison block and the third information input of the control block and to the address m input of the memory unit, the clock input of which is connected to the output of the first element OR, the first input of the first element OR to the first output of the synchronization unit, the second output of which is connected to the second input of the first OR element and to the input of the first delay element, the output of the first delay element - with a counting input of the counter, the output of the first element AND through the element NOT - with the input

Description

counter recording, zero output of the first trigger — with the stop input of the micro-operation unit and the inhibit input of the comparison block and the stop input of the synchronization block, the third output of which is connected to the resolution input of the comparison block, the output of the comparison block — with the first inputs of the second and third elements, tone KPI, the second inputs of which are connected respectively to the outputs of recording resolution and the start of waiting for the micro-operation unit, the output of the second element OR is connected through the second delay element to the input of the first unit The AND elements, the output of the third element OR through the third delay element - with a single input of the first trigger, the single output of the first trigger - with the second inputs, the third block of And elements, with the second input of the first And element, with the resolution inputs of the control unit and the synchronization unit, the start input which is the start input of the device, the output of the control unit is connected to the first input of the fourth element OR, the second input of which is connected to the output of the end of the microprogram of the micro-operation unit of the microoperation, the output of the fourth element OR from union of a stop input sync block, the output end of the block portion forming micro connected

to the third input of the first .utnw.frro if, the input of which is connected by f; The second floor of the third element OR is connected to the start and end of the device, the output of the fifth element OR is connected to the zero inputs of the first and second triggers, the single input of the second trigger is connected to the micro-operations block.

2. The device of claim 1, wherein the block for forming micro-operations contains four elements AND and one element OR, the stop input of the block is connected to the first inputs of the first, second, third and fourth elements AND, the inputs of the microprogram end block, the conclusion of the cycle, micro-operations and the end of the section are connected to the second inputs of the first, second, third AND elements and the first input of the OR element, the input of the beginning of the waiting block is connected to the second 1 inputs of the fourth AND element and the OR elements, first, second, tr tego fourth AND gates and OR gates are respectively vkodami end firmware encapsulating cycle microoperations beginning and end of the idle unit firmware.

I

The invention relates to automation and computer technology and can be used as a computer control device and other systems.

Microprogrammed devices with self-control are known, containing a microinstruction memory block with address and microinstruction registers, a microoperation formation unit, and a control unit P and 2.

The disadvantages of these devices are the large volume of the microinstructions memory block, the large amount of time spent on preventive control and the low reliability of operation.

It is also known a self-monitoring firmware with two microinstructions memory blocks, two address registers, two 5 address formers, two microinstruction registers, two counters, two microoperation formation units, two control units, two comparison units, two return address registers, Trig10 heras, elements AND, OR, and NOT 3 3 The disadvantages of this device are the great complexity caused by the two-channel principle of device construction, and also, the reliability of operation is low 15.

The closest in technical essence and achieved reza. Part 3 to and; B1 0G:; gp10 n1 Ya1tsch instant. roprsg1amnnoo.  arrangement of etching with a control, containing an AND block, a NOT element, two AND elements, two RS-trngters. , counter, address register, memory block, microinstructions register, control unit, microoperation formation unit and microinstruction address generation unit, the output of which is connected to the informational BXO address register house, the address register installation head is the first input of the device, the memory block output connected to the register input of micro-commands, the first output of which is connected to the first information input of the control unit, as well as to the first information input of the micro-operation unit, the first output of the micro-operation unit The operation is the first output of the device,. the second output of the microinstruction register is connected to the second information input of the control unit, as well as to the first information input of the microinstruction address generation unit, the second information input of which is the second input of the device, the control input of the microinstruction address generation unit is connected to the zero output of the first trigger, zero output the second trigger is connected to the first input of the first element AND, the counter outputs are connected to a group of inputs of the second element AND, the main mode of operation of the known device is ochsh mode in which reading is effected from a microinstruction storage unit, and issuing them through the block forming mikrooper functions on the control object.  At the moments of a simple device, caused by waiting for the end of the formation of a log of 1 conditions or the end of execution of microcommands by the control object, the device operates in the natural standby mode and at the same time performs a control read of microcommands from the memory block in order of increasing the number of memory cells starting with that on which the test readout was terminated in the previous idle mode.  Moreover, the issuance of micro-operations to the control object is blocked, and the control unit monitors the absence of distortions in the read micro-command.  At the end of the firmware implementation, the idle mode is enforced. Ulf OSLSSGTV. V-OHTpO. ibtfOlt; reading those microcooma 1 micro micrograms that are oc. T; i. n) -ir checked during their stay in modes.  natural expectation.  When executing the next microprogram, the process of control of micro-commands is carried out, starting with the initial micro-command of this micro program 4 J.  However, the device has a low reliability of operation, due to the lack of equipment in it, which would establish the relationship between the control reading process and the process of implementing microcommands.  As a result, the device may lag the Microcommand control process from the process of their implementation when the microprogram is executed, which results in their being unchecked for execution, and therefore decreases the reliability of operation.  In addition, the device has a low speed, which is due to the lack of selectivity in the control of micro-commands, t. e.  by the fact that not only the microcommands that will be implemented are subject to verification, but also those that, due to the branching of the microprogram, do not enter into the branch implemented by it.  The purpose of the invention is to improve the reliability, reliability of operation and speed of the device.  The goal is achieved by the fact that a firmware control device containing an AND block, an NOT element, two AND elements, two RS flip-flops, a counter, an address register, a memory block, a micro-command register, a control unit, an micro-operation unit, and an address formation unit microinstructions, the output of which is connected to the information input of the address register, the input of the initial setup of the address register is the first input of the device, the output of the memory unit is connected to the input of the register of microcommands, the first output of which is connected to the first information input of the control unit, and with the first information input of the microoperations forming unit, the first output of the microoperations forming unit is the first output of the device, the second output of the micro-command register is connected to the second information input of the control unit and the first information input of the micro-xand address block, the second the information input of which is with the second input of the device, the stop input of the microcommand address generation unit is connected to the zero output of the first trigger, zero output second trigger — with the first input of the first element AND; the counter outputs are connected with the inputs of the second AND element, a comparison block, a synchronization block, three delay elements of the five OR elements, two AND blocks and an OR register block are entered. with the first inputs of the first and second blocks of elements AND, whose outputs are connected to the information input of the counter and the first input of the block of elements OR, respectively, the output of the counter is connected to the first information input of the comparison block and the first input its block of elements AND, the output of which is connected to the second input of the block of elements OR, the output of the block of elements OR is connected to the second information input of the comparison unit and the third information input of the control unit and to the address input of the memory block, the clock input of which is connected to the output of the first element OR, the first input of the first element OR is with the first output of the synchronization unit, the second output of which is connected to the second input of the first OR element and and the input of the first delay element, the output of the first delay element with the counting input the output of the first element And through the element NOT with the input of the record of the counter, zero zero of the first trigger with the input of the micro-operation unit and the input of the prohibition of the comparison unit with the input of the synchronization unit, the third output of which is connected to the resolution input of the comparison unit, the output of the comparison unit - with the first inputs of the second and third elements OR, the second inputs of which are connected to the recording resolution outputs and the start of waiting for the micro-operation unit, the output of the second element OR through the second delay element is connected to the second input of the first block of elements, the output of the third element OR via the third delay element — to the single input of the first trigger; the single output of the first trigger — to the second inputs of the third block H1 1, and the second INPUT 4 of the first element AND, with the control unit and synchronization unit resolution inputs, the start input of which is the device start input, the control unit output is connected to the first input of the fourth OR element, the second input of which is connected to the microprogram end output unit and the formation of micro-operations, the output of the fourth element OR is connected With; the sync block stop input, the output of the end of the micro-ops forming unit section is connected to the third input of the first element AND whose output is connected to the first input of the fifth OR element, the second and third inputs of the fifth OR element are connected respectively to the start and end wait inputs of the device, output n That element OR is connected to the zero inputs of the first and second triggers, the single input of the second trigger is connected to the output of the beginning of the waiting block, the formation of microoperations.  The microoperation formation unit contains four AND elements and one OR element, and the block stop input is connected to the first inputs of the first, second, third and fourth AND elements, the microprogram end block, cycle conclusion, micro-operations block inputs and the end of the section are connected to the second inputs of the first and second, respectively. and the third element AND and the first input of the OR element, the input of the beginning of the waiting block is connected to the second inputs of the fourth AND element and the OR code, the codes of the first, second, third, fourth AND elements and the element and OR are, respectively, the outputs of the end of the microprogram, the loop termination, the micro ops, the start of the wait and the end of the microprogram of the block.  The essence of the invention is to increase the reliability of the operation of the device due to the advance control of micro-instructions in relation to the process of their implementation, as well as to increase the speed of the device by ensuring the selectivity of the process of controlling micro-instructions, i.e., excluding those that are not included into a realizable firmware branch.  7r Introduction of j ropoio b. The CEC of the elements of the AND and the bypass of the ILR1 elements and the conditional and No. 1 connections allows, by signals from the cool and single outputs of the first trigger, to control the feeding of the address of the microcommand from the address register or from the counter to the address input of the memory block, as well as to the second and third information inputs of the comparison unit and the control unit.  The introduction of the first OR element, and the relations it caused, is necessary to form the read signals at the clock input of the memory unit.  The introduction of the comparator and its associated links is necessary to verify that the next microcommand to be implemented belongs to the multitude of microcommands that were checked during the execution of the microprogram.  The introduction of the second OR element and its associated links is intended to generate a gadres transmission control signal from the output of the address register to the information input of the counter at the moment the device enters the forced control mode or at the time the microcommand completes which closes a loop in the firmware.  The connection of the output of the address register with the group of information inputs of the counter through the first block of elements And is intended to control the transfer of the address code from the address register to the counter.  The introduction of the second delay element is necessary to ensure the delay of the signal transmission of the address from the register to the counter for the time required to form the address of the next microcommand, which needs to be switched to, and the time of recording of this address in the address register.  The introduction of the first delay element and its associated connections is necessary for delaying the counter in the monitor mode by the time it takes to read the microcommand from the memory block, write it to the microcommand register and check it with the control block.  The introduction of the third OR element and the links due to it is necessary to form a signal at the single input of the first trigger to switch the device to the control mode if the control of microinstructions lags r: p | PO- ,.   implementation, either in the event.  PMP;) micro-instructions, i) an e-mail hank of waiting.  The introduction of the third element of the back link and its associated connection is intended to ensure the delay of switching of the first trigger to the unit state by the time required for switching the unit state of the second trigger when introducing the mode of control of the state of natural waiting.  The introduction of the fourth OR element and the connections conditioned by it is intended to form and output to the fourth control input of the synchronization unit a signal for stopping the operation of the device or at. detection of an error in a controlled microcommand, or when executing the final microcommand of a microprogram.  The introduction of the fifth SHW element and the relations determined by it is intended to form a signal to put the device into operation mode at the moment of either launching the microprogram or ending the wait for the microcommand, or when such a microcommand is reached (in the control mode in the natural standby state), which has a mark of the beginning of the wait, or the end of the linear section.  The connection of the fifth output of the microoperation formation unit with the third input of the first element I is intended to transmit a signal to transfer the device from the forced control mode to the operating mode when reading a microcommand having a mark of the start of waiting for the end of the linear section.  The introduction of the synchronization unit and the links conditioned by it is intended to form clock pulses of the operating or control frequency depending on the operating mode of the device, as well as control the operation of the comparator unit.  The connection of the zero output of the first trigger with the control input of the Microoperation Formation block is designed to control the output of signals to the first, second, third and fourth outputs of this block.  The connection of the single output of the first trigger with the second input of the first element I is intended to control the formation of a signal on the transponder device from the forced control mode to the operating mode.  The connection of the output of the second element AND through the element NOT with the control input of the counter is intended to control the operation of the counter.  Thus, the introduction of these elements and connections allows to increase the reliability of the function and speed of the device.  FIG.  1 shows a functional diagram of the proposed device; in fig.  2 is an example of a specific implementation of a functional contol block; ya fig.  3 is a functional block diagram of the formation of microoperations; in fig.  A - functional block synchronization circuit; in fig.  5 is an example of a specific implementation of the functional scheme for forming the microcommand address; in fig.  6 is an example of a specific implementation of the functional block of the comparison block for a three-bit address; in fig.  7 shows an example of dividing a microprogram into linear parts of their ranking and sequential numbering of microcommands.  The device (FIG.  , 1) contains the first block 1 of the elements AND, the first element 2 of the delay, the first element OR 3, the counter 4, the second element AND 5, the element NOT 6, 7 addresses, the block 8 of comparison, the second 9 and the third 10 blocks of the elements And, block 11 elements OR, memory block 12, microcommand address generation unit 13, microcoman register 14 with control field 15 and address field 16 and logic conditions, control unit 1, microoperation formation unit 18 containing the following outputs: microprogram end 19, microprogram end, output 20 tags Loop loop, output of 21 micro-operations signals, exit 22 tags Start of wait, exit 23 marks End of section, second 24 and third 25 elements OR, second trigger 26, third delay element 27, first element AND 28, fourth element OR 29 second delay element 30, fifth element OR 31, block 32 synchronization, the first trigger 33, informational 34 ,.  counting 35 and stopping 36 meters of counter 4, output 37 of counter 4, input 38 of the initial installation, which is the first input of the device, and 1510 information input 39 of the register 7 address, output. 40 address register 7, a group of outputs 41 elements OR of a block 11 elements OR, an output 42 of a comparison unit 8, a clock input 43 of a memory block 12, an information input 44 of a microcommand register 14, a second input 45 of a unit 13 of an address generator, which is the second input of a device . the first 46 and second 47 outputs of the register 14 microinstructions, the output 48 of the control unit 17, the fourth 49 and the second 50 outputs of the microoperation formation unit 18, the first 51 output of the microoperation formation unit 18, which is the first output of the device, the third 52 and the fifth 53 outputs of the unit 18 forming micro-operations, the third device input 54, the second input 55 of the fifth element OR 31, which is the fourth input of the device | Ba, the fourth control input 56 of the first synchronization 32, the third 57, the second 58 and the first 59 outputs of the synchronization unit 32, is single and 60 zero 61 outlets first th trigger 33.  Control unit 17 (FIG.  2) contains the first 62 and second 63 modulo-two adders with inverse outputs, the element OR 64, and the element AND 65.   The microoperation formation unit 18 (FIG.  3) contains the first 66 and second 67 elements And, the block 68 elements And, the third element And 69 and the element OR 70.  The synchronization unit 32 (FIG.  4) contains an RS flip-flop 71, a first 72, and a second 73 AND elements and a controlled oscillator 74, consisting of two alternators 74. 1 and 74. 2  The block 13 of the formation of the address of micro-commands (FIG.  5) contains block 75 multiplexers and block 76 elements I.  Comparison unit 8 (FIG.  6) contains the first 77 and second 78 blocks of elements NOT, the first 79 and second 80 elements OR, the first element AND 81, the third 82 and fourth 83 elements OR, the second element AND 84, the fifth 85 and sixth 86 elements OR, the third 87, the fourth 88, the fifth 89 and the sixth 90 elemenphs AND, the seventh element OR 91, the seventh element AND 92, the eighth 93 and ninth 94 elements OR, the eighth element AND 95, the group of outputs 96 of the first b. Until 77 11 elements of the European Championship, the group of output 97 BTQ poio block 78 elements is NOT.  FIG.  7 pos.  1-17 are the order numbers of m1-1 scopes in the microprogram, pos.  O - IV - the ranks of the linear sections of the microprogram.  The format of each firmware is conventionally shown in the form of rectangles.  The symbol KU means that in the corresponding area of the micro-command the mark is placed. End of the section with which the micro-commands of the end of the linear section are marked.  The BUT symbol means that in the corresponding zone of the micro-command, the Start of Wait label is placed, indicating that after the implementation of this micro-command, the device will enter the state of natural waiting.  The symbol ZZ means that in the corresponding zone of the micro-command there is a label. A loop closure, which marks the initial micro-commands of the return linear sections.  The symbol E means that a mark is placed in the corresponding zones of the micro-command that marks the final microcommand of the microprogram.  A dash means the absence of information in the zones of the listed marks.  The elements of the device have the following purpose (FIG.  one).  Unit 1 of elements I is designed to control the transfer of the microcommand address from address register 7 to counter 4 The address of the next microcommand to be implemented is rewritten into counter 4 during the process of entering the forced control mode.  The delay element 2 is designed to delay the clock pulses of the control frequency received at the dynamic input 35 of the counter 4 by the time f required to read the microcommand from the memory recording unit 12 into the microcommand register and check it with the Tg, control unit 17.  At the same time, the ratio + RG14 + 6K is valid. The element OR 3 serves to form the read signals at the clock input 43 of the memory unit 12.  Counter 4 is designed to store the address A, the next microcommand to be monitored during the implementation of microprogram microprograms, t. e.  in the operating mode, ia also forms the address A by the queue of the center; h1rm (P (pt g h-Mgms in the monitoring process.  The voice input 34 is intended for a parallel recording of the address of A pit, the alternate microcommand to be implemented, and the address received from the register 7 of address upon the introduction of the compulsory control mode.  This allows to achieve the selectivity of the compulsory control, t. e.  provide verification of only those microinstructions that are to be implemented.  In the process of monitoring microprojects of the microprogram, the address A of the next monitored microcommand is formed by increasing the code set in counter 4 by one when the counter clock frequency of the control frequency arrives at the counter input 35.  In order to avoid re-checking of already tested microinstructions, when counter 4 is reset as a result of its overflow by the zero signal at its input 36, it is prohibited to count the counter of 4 clock pulses of the control frequency received at its counting input 35.  Element AND 5 serves to fix the moment of filling of counter 4 in order to prevent its zeroing due to overflow.  When the counter 4 is filled, the output of the element 5 appears a signal that prohibits the counting of the control frequency pulses by the counter.  The element NOT 6 is d. n control counter 4, the register 7 addresses serves to store the address of the microcommand to be implemented, and issue it to the inputs of the elements 1 and 9.  The input 38 of register 7 is intended for the initial setting of the address AQ of the initial microprogram of the microprogram.  The input 39 of the register 7 is intended for parallel writing to the register 7 of the code of the next address generated by the address generation unit 13.  Comparison unit 8 is designed to check whether the next microcommand to be implemented is included in the number of microcommands checked during the implementation of the microprogram. Verification is performed by comparing the working and control addresses.  In this case, the control and work address is the address of the next microcommand, subject to 13. t according to control or implementation.  This principle of verification is possible provided that the coding of addresses of micro-commands is implemented in accordance with the principle of ranking microprogram line sections and the sequential numbering of micro-commands for each section so that micro-commands for higher-ranking sites and large serial number.  This number, represented in the binary system, is the address code of this firmware.  The convergence micro-command is understood to mean such a micro-command, to which within the limits of this microprogram it is possible to switch from two or more other various micro-commands.  The branch microcommand should be understood as such a microcommand, from which it is possible to move on to two or more other different microcommands different from itself.  In this case, the linear section of the program is called such a sequence of microcommands of this microprogram, which does not contain branching microcommands, except for the end ones in this section, and does not contain convergence microcommands, except for the initial ones in this section.  The rank of a linear segment is the largest number of linear segments located on the path from the beginning of the microprogram to the beginning of this segment.  When ranking sections of the firmware, its return linear sections should be broken at the points of loop closure.  By returnable linear portion of the microprogram, one should understand such a portion that leads to the formation of a cycle in the micro program.  An example of dividing a microprogram into linear sections, their ranking and sequential numbering of microcommands is shown in FIG.  7    In unit 8 of the comparison, the control A is compared (and the working, addresses).  If the next microinstruction to be implemented is unchecked, then it is executed. the ratio Cl + 1 PU n at the output 42 of the block 8 appears, by which the device is transferred to the j 5 V mode of the forced control.  An example of a specific implementation of the comparison unit 8 is shown in FIG. 6  The HE elements 77 and 78 of the compare unit 6 are designed to obtain the return code of the control and working addresses, respectively.  Groups of elements ШШ 79 and 80 and element И 88 of block b are intended for д. n forming the signal R1 of the equality of the first bits of the address codes received at the inputs 37 and 41 of the block.  When the first bits are equal, element 88 opens with single signals from the outputs of elements 79 and 80 of block 6.  Similarly, the set of elements OR 82 and 83 and the element AND 89 -block 6, as well as the set of elements OR 85 and 86 and the element And 90 of block 6 are intended to form equality signals R 2 and R 3, respectively, of two and three bits of address codes.  At the same time, the signal R 3 of the equality of the three bits of the codes at the output of the element AND 90 is formed according to the equality of the third bits, t. e.  on single signals from the outputs of elements OR 85 and 86 of the block, taking into account the signal of equality of the two previous bits (R 2) of the input element And 90s of the output element And 89.  Element 81 of block 6 is intended to form a signal Ml that the first bit of the working address is greater than the first bit of the control address.  Element 84 (87) of block 6 is intended to generate a signal that the second (third) bit of the working address is greater than the corresponding bit of the control address, and the number corresponding to the previous bit of the working address is not less than the number represented by the corresponding bits of the control addresses.  Element 92 of block 6 is intended to form signal 2 that the value of both the first and second bits of the working address is not less than the values of the corresponding bits of the control address.  Element OR 93 (91) of block 6 is intended to form the signal F 2 (F 3), indicating that the code of the two (three) bits of the working address is greater than the code of the two (three) corresponding bits of the control address.  Element And 94 of block 6 is designed to form the NIN-Hajbri, c; ridetel (; most of Bi; uri; inHP-H4n sogistlenm Lr,, L;,. ,,,.  Element AND 95 of block 6 controls the output of the comparison result to output 42 of block 6.  The blocks of elements AND 9 and 10 and OR 1 of the device are used to control the transfer of the address of the microcommand read from block 12 of the microcommand from the output of register 7 to the address or from the output of counter 4 in the working mode and in the monitoring mode, respectively.  The memory unit 12 is designed to store microprogram microprograms.  When a pulse arrives at the clock input 43 of memory 12, the microcommand is read at the address that arrives at the address input of the memory from the output of the block 11 of the OR elements.  In the microcommand format recorded in the memory block, the following zones can be distinguished: the zone of logical conditions in which the codes of the checked logical conditions are specified; an address zone intended to specify an unchangeable part of the address of the next microcommand; label zone The end of the firmware, which is marked with the micro-command, which is the latest in the firmware; label zone. A loop closure that marks micro commands, which, if implemented, can be used to re-execute an already implemented micro program section; the micro-operations zone, in which the micro-operations code is set; the area of check bits, in which the coding by the unit of the first bit is supplemented to an odd number of units in the microcommand, and the coding unit in the second discharge of this zone is set to correspond to the microcommand to the address at which it was read; label zone The start of the wait, which marks the microinstruction that sets the state of natural expectation; label zone The end of the section that marks the microcommands that terminate the linear sections of the microprogram.  The micro command address generation unit 13 (FIG.  5) is intended to form a working address, t. e.  addresses of the next microcommand to be implemented.  The information in block 13 enters its information input from the floor 16 of the register 14, 15fi where the contents of the cies zone and the logical conditions of the microcommand are written.  The content of the address zone is fed from the input of block 13 to the block of elements AND 76, which control the transfer of the address from block 13.  The modifiable part of the address is formed by a multiplexer unit 75, which checks the values of those logical conditions of the read micro-command, and is fed to the input 45 of unit 13.  The modified part of the address formed by the multiplexer unit 75 is appended to the unchanged part as the low-order bits.  The delivery of the generated address to the output of block 13 is allowed only if there is a single signal at its control input, t. e.  only in operation.  Register 14 of microcommands of the device is designed to store a microcommand read from memory block 12. In register 14, two fields can be distinguished: control field 15 and address 16 field and logical conditions.  Field 16 stores the contents of the address zone and the logical condition zone of the micro-instruction.  This information is used to form the working address Ap, 4, ... e.  Addresses of the next microinstruction, under, the underlying implementation.  The control field 15 stores the contents of the label zones I End of the microprogram, Start of the wait, Loop loop, End of the section, as well as the zones of micro-operations and the zone of check bits.  This information is used when generating a scientific research institute of device operation control signals, as well as micro-operations signals.  In addition, information from the outputs of fields 15 and 16 of register 14 enters control unit 17 for verification.  The control unit 17 is designed to check for the absence of errors in the micro-command recorded on the register 14, and to verify its compliance with the address at which it is read from the memory unit 12.  The operation of the control unit 17 in the operating mode is prohibited by a zero signal arriving at the control input from the output of the operating mode trigger 33.  As one of the possible options for implementing the control unit, a circuit can be used (FIG. 2), in which the modulo-2 adder 62 with an inverse output is intended to check the compliance of the tested 17and microcommand with that address, it is read.  The adder 63 modulo 2 with inverse output is designed to control the parity of the microcommand recorded in register 14.  The OR element 64 of the control unit 17 is designed to generate an error detection signal.  Element AND 65 of block 17 controls the generation of an error detection signal. to exit 48 block.  Block 17 works as follows.  The adder 63 produces the parity of the microcommand recorded in register 14.  The addition of the code of a micro-command with an even number of units to an odd one is made by recording when encoding a unit in the first discharge of its check digit zone (in FIG.  2 is indicated by the symbol 15-).  With an odd number of units in the micro-command code, zero is written in this bit.  If the number of ones in the code of the micro-command received for testing is even, then a single signal appears at the output of the adder 63 indicating an error in the micro-command.  In adder 62, the modulo 2 totals the number of units of the code of the control address and the value of the second bit of the area of the check bits of the microcommand (in FIG. 2, this bit is denoted by the symbol 15 - (+1). The coding of this bit is dependent. on the number of units in the code of the address of this micro-program.  If the number of units in this code and in the second bit of the check digit zone of the microcommand is even, then the output of the adder 62 modulo 2 is a signal indicating that the microcommand does not match the address at which it was read.  Signal output of control results from the outputs of adders. 62 and 63 through element 64 at the output 48 of the block is permitted only when a single signal is present at the input 60 of the block, t. e.  when the device is in control mode.  The micro-operation unit 18 for forming the device is intended for generating control signals for the device and the control object.  An example of a specific embodiment of block 18 is shown in FIG.  3  To the input 46 of the block comes from the field 15 of the control of the register of micro-commands the contents of the next 8 pcs of NfliKpoKOMannM; label zone 19 End of MHKponporpaMNfbi, label zone 20 Loop loop, zone 21 micro-operations, label zone 22 Start waiting and label zones 23 End S acTKa.  Element And 66 of block 18 is designed to control the output of a signal about the presence of a microcode command in the End of Firmware program, and element 67 of a signal about the presence of the label Close loop.  Block 68 of the And elements is intended to control the output of control signals of the control object.  Element And 69 of block 18 is designed to control the output to block 52 of the signal about the presence of a label. Start of wait in a microcommand.  The output of control signals by the device to outputs 49-51 and 53 and the control object on the output 51 of the device in control modes is disabled by a zero signal from output 61, trigger 33 (Fig.  1) arriving at the input 61 of block 18.  The element OR 70 of the unit 18 is designed to form a signal to put the device into operation during the control of a microcommand containing in the zone 22 the Start-up mark or in the zone 23 the End-segment mark.  I Element OR 24 of the device is used to form a signal that resolves the rewriting of the working address А pi from register 7 of address to counter 4 in case of a signal from the output 42 of the comparison block 8 to enter the forced monitoring mode and the loop signal from the loop 50 coming from output 50 block 18 forming micro-operations.  .  The OR 25 element is to generate a signal for switching the device to the monitoring mode in case of a signal coming from the output 42 of the block 8 to introducing the forced monitoring mode and a signal from the output 52 of the forming unit 18 to switching the device to the natural standby state when implementing the microcommand, containing the start of wait label.  This ensures a constant advance of the process of control of micro-commands in relation to the process of their implementation.  The trigger 26 of the standby mode serves to set the state 1911

PIA natural expectation device. Switching a trigger to a single state corresponding to the natural standby state is performed by applying to its S input a single signal from the output 52 of block 18 when implementing a microcommand setting the natural waiting state. Setting the trigger 26 to the zero state corresponding to the operating mode of the device is effected by the End of Wait signal from input 55 of the device.

The delay element 27 serves to exclude the signal of the start of waiting from the output 53 of the block 18 to the zero inputs of the flip-flops 26 and 33 when the -control mode is entered in the state of natural expectation. The time Cj, the signal delay for switching the device to the monitoring mode is determined by the time that the device enters the natural standby state, i.e. time ITjg installation trigger 26 0 unit state, and.

 .

27

Element And 28 of the device serves to generate a signal to transfer the device from the forced control mode to the operating mode by the signals of the Start of Suspend or End of Section signal.

The element OR 29 is used to form a signal to stop the operation of the device when it appears at the output. 48 of the unit 17 control unit indicating the detection of an error in the controlled microcommand or inconsistency with its address at which it was read, and also when a signal from the output 49 of block 18 appears when implementing the latest microprogram of the microprogram (by the End of microprogram ) A single signal from the output of this element sets the trigger 71 of the synchronization unit 32 (FIG. 4) to zero state, the zero signal from whose output prevents the operation of the comparator device 8 and the output of the clock pulses .

The delay element 30 serves to delay the signal to transfer the address from the address register 7 to the counter 4 by the time t JQ required to form () the working address, i.e. the addresses of the next microcommand, the implementation of which needs to be taken

15-H

and time L, “th transfer to the address register. This is true

-sixteen

The element OR 31 is used to form a signal for switching the device from the control mode to the operating mode when the AND 28 signal arrives from the output of the device to transfer the device to the operating mode from the forced control mode, as well as when the signal arrives at input 55 of the device.

The synchronization unit 32 (FIG. 4) is designed to generate clock pulses of the operating and control frequencies. In addition, the signal from its output 57 permits operation of block 8. Block 32 operates in two modes: operating and monitoring. The operation of the block in these modes is resolved with the arrival at the input of the device 54 of the Start pulse, which sets in one state the trigger 71, which enables, depending on the enable signal on the inputs 60 or 61 of the block, the generation of control pulses controlled by the generators 71.1 or 74.2 working frequency respectively. The simultaneous occurrence of signals at control inputs 60 and 61 is eliminated, since they come from the single and zero outputs of the trigger 33 of the operation mode. In addition, the signal from the single output of the trigger 71 of the block 32 arriving at its output 57 enables the operation of the block 8 of the comparison.

The trigger 33 serves to set the mode of the device. Its single state corresponds to the control mode, and the zero state corresponds to the working mode.

The device operates as follows.

In operation of the device, the following modes are distinguished: the operating mode in which the microprogram microprograms are implemented; the control mode in the state of natural expectation, entered with a simple device, due to the time spent on the formation of the values of logical conditions, the processing of microinstructions applied to control objects, etc .; forced control mode, entered by force to perform advanced control of micro-instructions by means of their control reading. 21 In the control modes of the PTC, the microinstructions are pinned down, during which microcommands are checked for the absence of distortions in them, without arriving at the output of the device. For the process of controlling microinstructions in the proposed device, the advancement of the process of their implementation, as well as selectivity, is characteristic. The first means that during the execution of the firmware, each microinstruction is realized only under the condition that it has already been tested during the execution of this firmware. The second means that those microcommands of the executed microprogram that cannot be included in the number of realized ones can be excluded from the number of controlled ones. The advanced nature of the control of micro-instructions in relation to the process of their implementation is provided by the comparison unit 8, which, in case of non-fulfillment of the conditions of advance, transfers the device to the forced control mode in order to eliminate the lag in koitrol, the selective nature of the control of micro-instructions is ensured by the transition to the implementation of the new linear section of If the microcommand control process lags behind the process of their implementation, microcommand control starts from the beginning of this particular segment. The untested microcommands of other linear sections that are not implemented are thereby excluded from the number of controlled ones ;. The operation mode of the device is set by triggers 26 and 33. llx corresponds to the zero state of the operating mode, single state - the control mode in the state of natural idle. The zero state of the trigger state 26 and the unit state of the trigger 33 correspond to the forced control mode. In the initial state, in the micro-command register a zero code is written, and in counter 4 and register 7, the address A of the initial micro-command of the firmware being executed. At outputs 58 and 59 of block 32, there are no clock pulses, i.e. its trigger 71 (Fig. 4) is in the zero state. The device triggers 33 and 26 are in the one and zero states, respectively. 1522 which corresponds to the pemtitfy of the regulatory control. With this cool signal from the output 61 of the trigger 33 for -1, the operation of the synchronization unit 32 in the operating mode, the output by the Ormacium by the micro-operation unit 18 at the outputs 49, 50 and 52 of the unit and the output 51 of the device, the output of the address generated by the block 13 is closed, block 9 of AND elements, as a result of which the receipt of the address from register 7 to the input of memory block 12 and input of block 8 is prohibited. A single signal from output 60 of operating mode trigger 33 allows operation of control unit 17 and opens block 1 of AND elements, as a result of which transmission is allowed addresses from p Register 7 addresses in the counter 4. In addition, the same signal allows the block 32 to operate in the control mode and opens the block 10, resulting in the receipt of the address of the microcommand, the control of which produces | from the output 37 of the counter 4 to the input of the control and the input of the block 12 memories. The operation of the block 8 in this case is prohibited by zero signals from the output 57 of the block 32 and the output 61 of the flip-flop 33. The initial installation circuits of the indicated elements of the device in FIG. 1 conventionally not shown. The impulse Start, coming from the input 54 of the device to the input of the block 32, the device begins to work in the mode of forced control. In this case, the trigger 71 is set to one (Fig. 4), allowing the output of the control frequency clock to the output 58. The output from the output 57 of the block 32 allows the operation of block 8, but the output of the comparison result to its output 42 is prohibited by the zero signal the output 61 of the trigger 33. When the clock pulse of the control frequency arrives at the clock input 43 of the memory block 12, the microcommand is read to the address supplied to its address input from counter 4. The read microcommand is stored in register 14. The same clock cycles th pulse, which is produced by the reading unit 12 from the microinstruction memory for verification, but delayed by the element 2, on the time required for reading and controlling the microinstruction:, incremented by one code set in the counter 4, i.e., The address of the AC is set in the meter. for which the next one is a microcommand for control. The control unit 17 performs a check of the parity of the read microcommand, as well as checking its correspondence to the address at which it is read. If, as a result of the control of the microcommand, block 17 detects an error or inconsistency with its address, which is being read, then the signal is not the norm from the output 48 of block 17 coming through the OR element 29 to the control input (stop) 56 of the block 32 of synchronization, trigger 71 the block is set to the zero state. This prevents the generation of clock pulses. The device stops working. In the absence of errors with the arrival of the next clock pulse of the control frequency, the device operates in the forced monitor mode as described. If a micro-command is read from the 12th unit of control, containing the Start of wait or the End of the segment label, then the output from the 53 output of the microoperations forming unit 18 opens element 28, and the rest of the inputs are sent at this moment from zero and single outputs of triggers 26 and 33, respectively. The output signal of this element through the OR element 31 sets the trigger to the zero state. Thus, the device is switched to the operating mode, i.e. firmware implementation mode. In this case, the single signal from the output 61 of the trigger 33 of the operating mode resolves the operation of the synchronization unit 32 in the operating mode, outputting the result of the comparison of the working address Ap- (i.e., the address of the microcommand to be implemented) with the control address (i.e. the address of the microcommand to be monitored in the next control cycle), to the output 42 of the comparison unit 8, transmitting information by the microoperation formation unit 18 and the address generator 13. In addition, block 9 is opened to transfer the working address Api + 1 from register 7 to the input of block 12 and the input of block 8 of comparison. The zero signal from output 60 of three modes of operation 33 prohibits 15 operation of control unit 17 and closes block 10, as a result of which control address A ((i.e., address for which another microcommand is read for control) is denied) the counter 4 to the address input of the memory unit 12 and the input of the comparison unit 8. When a clock pulse of the operating frequency arrives from the output 59 of the synchronization unit 32 through the OR 3 element to the clock input 43 of the unit 12, a microcommand is read, starting with which the microprocessor continues grams. The address of this firmware is fed to the address input of memory block 12 from address register 7 through block 9. The read micro-command is recorded in register 14. The contents of control register 15's 15 field is fed to the information input of micro-operation unit 18, as a signal from output 60 of trigger 33 If information is transmitted to outputs 49 - 53 of block 18 (Fig. 3), then from the output of 21 micro-operations microcommands micro-operations signals are output to device output 51 to be implemented by the control object. The contents of the address field 16 and the logical conditions of the register 14 are fed to the information input of the address generator 13, where, taking into account the value of the logical conditions to be checked, applied to the device input 45, the address AR- + 1 of the microcommand to be implemented in the following tact is formed. The generated address is recorded in register 7, from the output of which is fed to the address input of the unit 12 and the information input of the comparison unit 8. In comparison block 8, the generated work address Ap; +1 is compared with the control address A coming from the output 37 of the counter 4. If, as a result of the comparison, it turns out that the next microcommand to be implemented is verified, i.e. the inequality Api., -. then this micro-command is read from the block 12 for the arrival of the next clock pulse of the operating frequency. The device works as described. 251 If, as a result of the comparison of the haddresses, it turns out that the next microcommand to be implemented has not yet been checked, i.e., the maintenance inequality is fulfilled at the output 42 of block 8 and a signal is generated that through the OR 25 element and the delay element 27 is set to one trigger 33. Thus, the device is transferred to the described forced control mode, which corresponds to the zero and one states of the triggers 26 and 33, respectively. With the same signal through the OR 24 element and the delay element 30 opens 1 and block elements, resulting in the counter 4 from the register 7 zapisgoaets address Ap i.i next microinstruction to be implementation and decoupling is untested. With this micro-command, further control of micro-commands begins. This achieves the selectivity of the control of micro-commands, since the recording of a new working address from register 7 to counter 4 according to the signal from the output of the comparison block 8 makes it possible to exclude from the number of verifiable microcommands that are not included in the implemented microprogram branch. Next, the device works in forced control mode. l is the same as at the beginning of the implementation of the firmware. If in the process of forced control, counter 4 sets the maximum possible address value determined by the upper boundary of the area of the used memory cells, then a signal appears at the output of AND 5, which, arriving at the input to stop 36 of the meter 4, prohibits the counting of clock pulses the frequencies arriving at its counting input 35. This eliminates the re-checking of already tested and implemented micro-instructions due to the counter counting 4, as a result of overfilling. In addition, with the label End of the section, which is necessarily placed in the corresponding zone of the micro command, having the highest possible address value, the device is put into operation mode as described. If, in the operation mode, the microcommand to be implemented and recorded in register 14 has the 1526 mark Start wait, then the output 52 of the micro forming unit 18 of the operations is a signal that sets the trigger 26 of the natural standby state to one. The same signal through the element OR 25 and the delay element 27 is set to one state trigger 33. The delay time of this signal is determined by the relation v - 2m 2b where is the trigger response time 26. The signal delay at the time allows to exclude the signal from the mark. zero inputs of the flip-flops 33 and 26 from the output 53 of the micro-operation unit 18 through elements 28 and 31, since by the time a single signal appears at the output 60 of the flip-flop 33, the And 28 element is closed by a zero signal from the zero-output of the trigger 26. I With the transition of the trigger 26 and 33 to the single state, the device enters the control mode into the state of natural expectation. The transition to this mode and operation in it is carried out in the same way as in the forced control mode, with the difference that the element 28 is closed with the zero signal from the zero output of the trigger 26, as a result of which the signals of the start of the waiting or the end of the section with output 53 of the block 18 to the zero input of the trigger 33. This excludes the transfer of the device from the control mode in the state of natural standby to the operating mode before the end of natural standby. In addition, if in the control process in the state of natural expectation. In the counter 4 the maximum possible value of the microinstruction address is set, then at the output of the element 5 there appears a single signal which, entering through the element 6 at the input 36 of the counter 4, prohibits counting clock pulses of the control frequency, arriving at its counting input 35, as a result, before the end of the control mode, a microcommand having the maximum possible address is checked in the state of natural expectation in each clock cycle. This eliminates the need to re-check (E pe .4yjTbTaTP roundup the meter when it overflows) to the uk of the tested microcontrollers.

The switching of the control unit of the control mode in the state of natural standby to the operating mode is carried out by the signal End of waiting. It is formed either by the control object at the end of the microcommand, or by a timer, which sets the execution time of the microcommand by the control object. The end of wait signal arriving at the device input 54 through the OR element 31 sets the triggers 26 and 33 to the zero state, as a result of which the device is put into operation.

If, during the implementation of the firmware, an microcommand containing the loop closure label is read from the memory block 12, the output from the output 50 of the microoperation formation block 18 through the OR 24 element and the delay element 30 opens the AND unit 1, resulting in counter 4 of the address register 7 is recorded by the address Ap of the microcommand to be implemented in the following operation cycle. The delay time of the ARM of the element 30 is determined by the time when the address of the AO microcommand is formed; minute and the time t

eh-o zyp in the register of the address 7, in

go

Writing a new working address from register 7 to counter U by the label Loop loop allows you to resume monitoring micro-commands, starting with the one specified by this address, and thus avoid implementing untested micro-commands in the course of further microprogram execution. It is obvious that at the end of the implementation of the micro-command, Marked with the specified label on the signal from the output 42 of the block 8, the device goes

in the forced control mode.

If, in the operating mode, from memory block 12 to register 14 of micro-instructions is read to implement a micro-command containing the end of microprogram label, then output 49 of block 18

a microoperation driver generates a signal which, entering through the OR element 29 at the input to the stop 56 of the synchronization unit 32, prohibits

Inch clock pulses. The device stops working.

Thus, the invention is more reliable than the known device, since it eliminates the possibility of a consumer of unreliable (untested) microcoma.

Speed performance is achieved by eliminating microcommands from control, not participating in the computational process at the moment.

(5s

e61 7

Fig

39

& 76

45

Claims (2)

1. A MICROPROGRAM CONTROL DEVICE containing a block of AND elements, an NOT element, two AND elements, two RS flip-flops, a counter, an address register, a memory block, a micro-register, a control unit, a micro-operation generation unit and a micro-instruction address generation unit, the output of which is connected with the information input of the address register, the input of the initial setting of the address register is the first input of the device, the output of the memory block is connected to the input of the micro-command register, the first output of which is connected to the information input of the control unit and from the first m is the information input of the microoperation formation unit, the first output of the microoperation formation unit is the first, the output of the device, the second output of the micro-command register is connected t to the second information input of the control unit and to the first information input of the micro-command address formation unit, the second information input of which is the second input devices, the stop input of the micro-command address generation unit is connected to the zero output of the first trigger, the zero output of the second trigger to the first input of the first element And, the outputs of the counter are connected to the inputs of the second AND element, characterized in that, in order to increase the reliability of operation, a comparison unit, a synchronization unit, three delay elements, five OR elements, two blocks of AND elements and a block of OR elements, are introduced into the device. moreover, the output of the address register is connected to the first inputs of the first and second blocks of AND elements, the outputs of which are connected to the information input of the counter and the first input of the block of OR elements, respectively, the output of the counter is connected to the first information input of the block comparing with the first input of the third block of AND elements, the output of which is connected to the second input of the block of OR elements, the output of the block of OR elements is connected to the second information input of the comparison unit and the third information input of the control unit and to the address input of the memory block, the clock input of which is connected to the output the first OR element, the first input of the first OR element - with the first output of the synchronization unit, the second output of which is connected to the second input. the first OR element and with the input of the first delay element, the output of the first delay element is with the counting input of the counter, the output of the first element AND through the element is NOT - with the input SU „„ 1104515 Π 00515 write the counter, the zero output of the first trigger - with the stop input of the microoperation forming unit and the inhibit input of the comparison unit and the stop input of the synchronization unit, the third output of which is connected to the enable input of the comparison unit, the output of the comparison unit - with the first inputs of the second and third elements, OR, the second inputs of which are connected respectively to the outputs of the recording permission and the start of waiting for the microoperation forming unit, the output of the second OR element through the second delay element is connected to the input of the first block AND elements, the output of the third OR element through the third delay element - with a single input of the first trigger, the single output of the first trigger - with second inputs, the third block of AND elements, with the second input of the first AND element,. with the permission inputs of the control unit and the synchronization unit, the start input of which is the start input of the device, the output of the control unit is connected to the first input of the fourth OR element, the second input of which is connected to the output of the microprogram end of the microoperation forming unit, the output of the fourth OR element is connected to the stop input of the unit synchronization, the output of the end of the section of the microoperation formation unit is connected to the third input of the first AND element, the output of which is connected to the input of the fifth OR element, the second and third heel inputs of the first OR element is connected to the start and end of the device standby inputs, the output of the fifth OR element is connected to the zero inputs of the first and second triggers, the single input of the second trigger is connected to the output of the standby start of the microoperation forming unit. 2. The device according to claim 1, wherein the microoperation forming unit contains four AND elements and one OR element, the stop input of the unit being connected to the first inputs of the first, second, third and fourth elements And, the inputs of the block of the end of the microprogram, the conclusion of the cycle, microoperations and the end of the section are connected to the second inputs of the first, second, third AND elements, and the first input of the OR element, the input of the standby start of the block is connected to the second inputs of the fourth element AND and the OR element, the outputs of the first, second the third, fourth AND elements and the OR element are respectively the outputs of the end of the microprogram, the conclusion of the cycle, microoperations, the beginning of the wait and the end of the microprogram of the block. 1 _