SU1096760A1 - Versions of group clock synczronizing device - Google Patents

Abstract

1. A group clock synchronization device containing a switch, the inputs of which are the information inputs of the device, a clock generator, a phase discriminator and a time code counter, to the input of which I connected the first clock generator output, which is so that, in order to reduce the time to synchronization, the series-connected adder of the time code, the block tam ti and the register, and also the constants sensor, the address counter, the element NOT and the series-connected shift block, an olusummator and an element whose output is connected to the input of the block recording, memory, the second output of the element AND is combined with the recording input of the shift block and is the recording input of the device, while the second output of the clock generator is connected to the inputs of the address counter and the element NOT, the output which is connected to the clock inputs BLR-. shift and register, and the output of the address counter is connected to the address inputs of the switch, the memory unit and the shift block, to the information input of which and to the information input of the half accumulator are connected the VYH9D switch, and the output of the half accumulator is connected to the clock inputs of the phase discriminator, to the second inputs of which are connected the inverse outputs of the time code counter, the direct outputs of which are connected to the inputs of the current time code of the time code adder to the inputs of which constants are connected to the outputs of the constant sensor, Exit phase discriminator and are half-adder output device. (L 2. A group synchronization device containing a switch, whose inputs are the information inputs of the device, a clock generator, a phase discriminator and a time code counter, to the input of which is connected a first clock generator output that is different that in order to reduce the time of entry into synchronism and increase noise immunity, the joint venture introduced a crushing elimination unit, a series-connected time code adder, a memory unit and a register, as well as a constant sensor, the NOT, the address counter and the series-connected shift block, the half-adder and the AND element whose output is connected to the write IN of the memory block, the second input of the AND element is combined with the write inputs of the shear block and the crushing section and the recording entry of the device This second clock generator output is connected

Description

to the inputs of the Address and Element Counter, the output of which is connected to the clock inputs of the shift unit, register and crushing section, and the output of the address counter is connected to the address inputs of the switch, memory unit, crushing section and the shift unit, to whose information input, also, the output of the elimination node of the crushing, the information input of which is connected to the switch output, is connected to the information input of the half adder, and the switch output is connected to the clock inputs of the phase discriminator, to the second inputs of the switch In addition, the inverse outputs of the time code counter, the direct outputs of which are connected, are connected to the inputs of which constants are connected to the outputs of the constant sensor, and the outputs of the phase discriminator are the outputs of the device.

3. The device according to claim 2, is distinguished in that the crushing elimination unit contains m shift blocks combined by address inputs and clock inputs, and the output of each block is connected to the information input of the subsequent shift block and to the corresponding adder input, the output of which is the output of the crushing assembly, the information input of which is the information input of the first shift unit.

The invention relates to communications and can be applied to match the operation of a multi-channel receiver with remote transmitters. | It is known a group synchronization device: a 5th synchronization, containing a generator, a transducer, the first input of which is connected to the output of the master oscillator, the second input is connected to the control output of the discriminator, and the other input connected to the input of the device, -a output to the input of the control element ij.

The drawback of the device is the complexity of its construction, since it has individual equipment for each channel (intermediate transducers and control elements).

Closest to the proposed 20 is a group clock synchronization device containing a switch, whose inputs are the information inputs of the device, a clock generator, a phase discriminator, and a time code counter, to the input of which a clock generator C2 is connected.

The disadvantages of the known group synchronization device 30 are a sufficiently long synchronization time, since synchronization is performed alternately on each channel, and low immunity, since synchronization within the message is present only for one channel, the information of the other channels is not synchronized and accordingly, there will be a mismatch between the receiver and the remote transmitter, and consequently, a decrease in the noise immunity of the received information.

The purpose of the invention is to reduce the time of entry into synchronism, as well as increase noise immunity.

This goal is achieved in that a group clock synchronization device containing a switch, whose inputs are device information inputs, a clock generator, a phase discriminator and a time code counter, to the input of which the first clock generator output is connected, is connected in series by a time code adder , a memory block and a register, as well as a constant sensor, an address counter, a NOT element, and a series-connected shift block, a half-adder, and an AND element, the output of which is connected The second input of the AND element is combined with the recording input of the shift block and is the recording input of the device, and the second output of the clock generator is connected to the inputs of the address counter and the HE element whose output is connected to the clock inputs of the block: Shift and register, and the output of the address of the address is connected to the address inputs of the commutator, memory unit and shift unit, to the information input of which and to the information input of the semi-adder the output of the switch is connected, and the output of the semi-adder is connected to the cycles th inputs of the phase discriminator, to the second inputs of which the inverted outputs of the time code counter are connected, the direct outputs of which are connected to the inputs of the current time code of the adder of the time code, to the inputs of which constants the outputs of the constant sensor are connected, and the outputs of the phase discriminator and half-sum (era are outputs devices. A group clock synchronization device containing a switch, the inputs of which are the information inputs of the device, a clock generator, a phase discriminator and a time code counter, to the input of which the first clock generator output is connected, has an elimination node, connected in series by a time code adder, the memory block and register, as well as the constant sensor, the element NOT, the address counter and the series-connected shift block, the half-adder and the element AND whose output is connected to The recording unit of the memory unit, the second input of the AND element is combined with the inputs of the recording of the shift unit and the deinterlacing unit and is the recording input of the device, while the second output of the clock generator is connected to the inputs of the address counter and the NOT element whose output is connected to the clock inputs of the shift unit , register and ysna eliminate crushing, and the output of the address counter is connected to the address inputs of the switch, the memory unit, the crushing section and the shift block to the information input of which, la also to the information input of half sums A node output is connected to the device. eliminating crushing, to the information input of which the output of the switch is connected, the switch output is connected to the clock inputs of the phase discriminator, the second inputs of which are connected to the inverse outputs of the time code counter, the forward outputs of which are connected to the time code adder , to the constant inputs of which the sensor constants are connected, the outputs of the phase discriminator being the outputs of the device. At that, the crushing elimination unit contains m shift blocks combined by address inputs and clock inputs, and the output of each block is connected to the information input of the next shift block and to the corresponding input of the adder, the output of which is the output of the crushing section, the information input of which is the input of the first block shift. Fig. 1 shows the functional diagram of the first variant of the group clock synchronization device, Fig 2, the same, the second variant of the group synchronization device (Fig 3) shows the signal timing diagram. Write to the memory block, Fig. 4 shows the timing diagram. synchronization of a multichannel receiver with remote transmitters; FIG. 3 is a timing diagram of the operation of a pulsed signal crushing block in an N-channel system. The group synchronization device in the first embodiment contains a switch 1, a counter 2 addresses, a generator of 3 clock pulses, a counter 4 of a time code, an adder 5 of a time code, a block 6 of memory, a register 7, a phase discriminator 8, a sensor 9 of constants, a block 10 of shift, the half-adder 11, the element 12, the element NOT 13, the shift block 10 contains the memory element 14 and the trigger 15. The group clock synchronization device according to the second embodiment comprises a switch 1, a counter 2 addresses, a generator 3 clock pulses, a counter 4 of the time code, an adder 5 time code, bl approx 6 memory, register 7 phase discriminator 8, onstant sensor 9, shift unit 10, half adder 11, element I12, element NOT 13, shift unit 10 contain memory element 14, trigger 15, crushing section 16, blocks 14fft the shift, the adder 18, each block 17 of the shift contains the memory element 19 and the trigger 20. The width of the address 2 counter is determined by the formula, where N is the number of information channels, k is the number of bit of the binary counter 2 addresses. The operation time of counter 4 of the time code. Is determined by the duration of two binary packages (for example, at speed: 1200 baud, it will be 832x2 1664 µs), since the detection of the signal on each channel is carried out by comparing the values of two time codes corresponding to the front of the received signal. The time diagram (Fig. 3) shows the operation of the device during the formation of a signal. Record in memory block 6 and the space-time method for receiving information. The input information (Fig. 3a) in the second embodiment over N channels is constructed by the space-time method on switch 1 in accordance with the address code, which is received cyclically from counter 2 of the address. On the front driver, which is derived from the shift unit 10 and the half adder 11, the fronts of the input signals are also formed in accordance with the address code with a shift in time and space. On the front of the signal from the time code counter 4, the current time code is read and a constant is added to the time code adder 5 on it. The resulting reference point in binary code is recorded in memory block 6. In the next cycle in the same address code, the previous value of the reference point reads off into register 7 and goes to the first inputs of the phase discriminator 8, the second inputs of which are fed to the inverse value of the current time code. In phase discriminator 8, the current time code is subtracted from the signal front from the binary code calculated in the previous cycle. Thus, in the phase discriminator 8, the mismatch between the current and the previous fronts of the initial code for a given address code and the detection of the initial code is calculated. The group clock synchronization device according to the first variant works as follows. 1 0 Address allocation to each channel is performed by a 2 address counter, to the input of which a clock series arrives from a 3 clock pulse generator, and an output code of each channel is generated at the outputs (Fig. 3a, b), so each code value corresponds to the connection of one channel and the cycle of code repetition corresponds to the cycle of accessing this channel (fig. 3d, e). Consequently, the input information from the N channels arriving at the inputs of the switch 1 is collected at the output into the group path for further processing in accordance with the individual address. At the individual addresses, information from the output of the switch 1 is recorded in the memory element 14 of the shift unit 10 by the Recording signal (Fig. 3g). In the next cycle, the Read signal (Fig. 3b) at the same address rewrites the previous information into the trigger 15 and from its output is fed to the input of the half-adder 11, to the other input of which the current information from the output of the switch 1 goes. Signal (Fig. 3g) at the same address, it is recorded in the memory 14 of the memory of the shift unit 10. A single signal will be present at the output of the half adder 11 if the preceding and subsequent information will have different values at its inputs (FIG. ZJ), which corresponds to the signal front at a given time position. On counter 4 is a time code that is L-bit binary. by register, different codes may be written. On the time axis (Figures 4 a, b, c, d) these codes can be depicted as a series of evenly distributed points filling the time axis with a specific repetition cycle, for ease of consideration, (fig. 4e) Consequently, each point on the time axis corresponds to a specific code value. If on the signal front to the corresponding time code add a constant, which is -. em 3/4 of the duration of an elementary binary parcel, and the result is compared with the time code corresponding to the subsequent front, it is possible to determine one or two times the duration of the received message (figure 4 with - shipment of a single length, figure 45 sending two times the duration). The presence of a single signal at the output of the phase discriminator (Fig. 4 hio the front of the input signal corresponds to a one-time signal of a single signal and a zero signal - a sending of a double duration. - The constant is selected, and the course of the possible distortions of the element sprinkling (Fig. 4a, b, c, d, d, e), the leading edge of the signal (figure 4 a) corresponds to the time code 1000, the constant on the counter 4 of the time code for a speed of 1.2 kHz will be 0110, the trailing edge of the signal (fig.4a) corresponds to time code is 1010. With the addition of 1000 + 1 1110, the reference point is the sum obtained the time axis determines the point relative to which the code corresponding to the subsequent front determines the duration of the parcel.When the dressing is distorted (Fig. 4a) less than 50%, it will be accepted as a one-time parcel. For this, you must subtract the time code of the subsequent front (figd-1010) or add its inverse value 1110 + Toooo t In the case of the output of the discriminator 8 there is a single signal (transfer) and thus a parcel of a single duration is fixed. Two parcels of a single duration correspond to a binary unit. Similar calculations can be made for the signal (fig.4b) leading edge time code 0100, constant 0110, subsequent edge time code 0101. When adding 0100 0001 f + 2119 1210 OOOT1011 transfer is absent In this case, the output phase discriminator present zero signal on the front of the input signal. therefore, a double-duration send is received, corresponding to binary zero. Hence, further transformation and reception of input information simultaneously over N channels with correcting power, tgk, as the shift of signal fronts less than 50% does not change the result of the determination of the duration of the parcels. The constant sensor 9 forms a constant in the form of a binary code, the value of which varies only with the frequency of the received information (1.2-2.4 kHz). For example, the input information comes in at 1.2 kHz (832 microseconds long), then a single parcel will be 4T6 microseconds, assuming that it is gated 4 times, the interval will be 104 microseconds, hence the switching frequency of the time code counter 4 614.4 kHz (104 µs duration). Consequently, the time code intervals will be τ 104 μs, then the interval from time code 1000 to interval 0100 will be 104 μs (Fig.4 c, d, d). The constant in this case is chosen 3/4 of the duration of the parcel and will be 0110 in the binary code, counting from 0000. In the proposed group clock synchronization device (Fig. 1,3,4), the time code and constant are summed up on the adder 5 of the time code, and the result recorded by the signal Record from the output of the element 12 in memory block 6 on the signal edge. In the next cycle by the signal Reading the output of the element HE from memory unit 6, the result is rewritten into register 7 and summed on the phase discriminator 8 with the inverse of the current time code corresponding to the subsequent edge of the received signal. There is a single signal at the output of the phase discriminator, when a parcel of a single duration is received along the fronts of the input signal, and when it receives a double-duration message on the fronts of the input signal, the signal is zero. The group clock synchronization device according to the second variant works as follows (FIG. 2-5). The distribution of addresses on each channel is carried out by a 2-address counter, to the input of which a clock series arrives from a 3-clock generator, and the address code of each channel is generated at the outputs of the 2-address counter so that each value (figure 5, c, d) is temporary positions of the 1st, 2nd and Lt channels of the code correspond to the connection of one channel and the cycle of code repetition corresponds to the cycle of accessing this channel. The input information from the N channels, going to the inputs of switch 1, is collected in the group path in accordance with with adress code From the switch 1 output, information on the time positions is recorded by a signal. Write to the memory element 19 of the 17.1 shift unit of the crushing unit 16. In the next cycle, the information with the readout signal is rewritten into the trigger 20 of the shift block 17.1, and with the write signal the current information is written into the memory element 19 of the shift block 17.1. In this case, the information of the previous cycle of the same time position is recorded in the memory element 19 of the shift block 17.2 from the trigger 20 of the shift block 17.1, etc. Thus, at the outputs of the 17.1, ... 17xJV shift blocks, there are samples of signals from one channel to a temporary position, which are summed on adder 18 with the addition of the previous value of the signal sample (Figures 2 and 5, e, f, g, and to). At the output of the adder 18 (Fig. 5l, mn, n, p, c), where single and zero impedances are shown separately for each channel for clarity, the splitting of the input signal is eliminated. Example 1. At t7 / 4, signal without splitting, “Block 17.1 shift 01111000 Block 17.2 shift 00111100 Block 17.3 shift 00011110 Block 17.h shift d00011.11 Totalizer output 18 00011110 PRI mme R 2. At tn 4, signal crushing. Shift block 17.1 0110100 Shift block 17.2 0011010 Shift block 17.3 0001101 Shift block 17.P1 00001 1 0 Totalizer output 0001110 0 From example 2 it can be seen that signal splitting is eliminated and information is present without fragmentation at the output of the adder 18. From the output of the adder 18, the information directly and through the shift unit 10 is fed to the inputs of half-adder 11, the output of which will contain a single signal if its previous and subsequent information have different values at a particular time position at the inputs, which corresponds to the signal edge at that time position (fig.Zt, y, f). Thus, in the proposed device, the current time code is summed with a constant on the adder 5 of the time code, the resulting sum in parallel code is recorded in memory block 6 by a 3-write signal in memory block 6, which is generated on the And 12 element by the edge signal and gated clockwise on record In the next cycle, at the same address, the sum of the time code plus a constant from memory block 6 is rewritten into register 7 by the Read signal and fed to the inputs of the discriminator 8, to the other inputs of which the current time code in the inverse code enters. At the output of the phase discriminator 8, a single signal is present at the front of the signal when receiving a message of a single duration, and when receiving a message of a double duration, a zero signal is received for the corresponding time position. In the proposed devices, a reduction in the acquisition time is achieved by the fact that the input information is processed on all channels within the sprinkling with the space-time method, whereas in the known device the synchronization is performed alternately on each channel. In addition, the absence of channel dividers and the presence of adders to determine the mismatch of the fronts of the input signals relative to the point of reference significantly reduce the time to synchronization, since each channel divider must be adjusted to the input information. Also, in the proposed devices, by eliminating channel dividers per channel, a correction pulse switch and a clock switch greatly simplify the circuitry of the device. If we assume that the channel divider has a division factor of 16, then one chip will be required for each channel and, therefore, in a known device there will be about 30, according to the number of channels, and since the proposed devices are calculated on average by 64 channels, it would be necessary to apply two one-type devices similar to the known one. In the proposed devices, there is an increase in input channels compared to the known. If you take time to work on one channel

Fig. 1, 1.63 ISS, which is quite acceptable, when the bits of the counter 2 addresses are sent, the bi-pulse signal with a duration of 416 μs is gated 4 times, and N the number of input channels will be N channels. In addition, there is an increase in the confidence factor, which is achieved by receiving fronts of signals with a shift in duration of less than 50%. It is also possible to receive information at speeds of 1.2-9.6 kHz, in which case the constant will have a specific value for each speed.

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Claims (3)

1. The device group clock synchronization, containing a switch, the inputs of which are the information inputs of the device, a clock generator, phase discriminator and a time code counter, in | which is connected to the first output of the clock generator, which means that, in order to reduce the time of entering synchronism, a time code adder, a memory unit and a register are introduced in series, D * also a constant sensor, address counter, element NOT and a series-connected shift block, a half-adder, and an And element, the output of which is connected to the recording input of the block. memory, the second output of the AND element is combined with the recording input of the shift unit and is the input to the recording device, while the second output of the clock generator is connected to the inputs of the address counter and the element NOT, the output of which is connected to the clock inputs of the unit. shift and register, and the output of the address counter is connected to the address inputs of the switch, the memory block and the shift block, to the information input of which and the information input of the half-adder is connected the output of the switch, the output of the half-adder is connected to the clock inputs of the phase discriminator, to the second inputs of which are inverted the outputs of the time code counter whose direct outputs are connected to the inputs of the current time code adder of the time code to the inputs of the constants of which the outputs of the constant sensor are connected, and the outputs phase discriminator and half adder are the outputs of the device. 2. The group clock synchronization device containing the switch,. the inputs of which are the information inputs of the device, a clock generator, a phase discriminator and a time code counter, to the input of which the first output of the generator is connected. a clock pulse thief, characterized in that, in order to reduce the synchronization time and increase noise immunity, a crushing elimination unit, a time code adder, a memory unit and a register, as well as a constant sensor, a NOT element, an address counter and a shift unit connected in series are introduced , a half-adder and AND element, the output of which is connected to the recording input of the memory block, the second input of the And element is combined with the recording inputs of the block. shift and the crushing elimination unit and is the recording input of the device, etc. said second output clock generator connected e 3 ”to the inputs of the address counter and the element NOT, the output of which is connected to the clock inputs of the shear unit, register and the unit for eliminating crushing, and the output of the address counter is connected to the address inputs of the switch, the memory unit, the unit for eliminating crushing and the shear unit, to the information input of which and also to the information input of the half-adder is connected the output of the elimination unit. crushers, to the information input of which the output of the switch is connected, and the output of the switch is connected to the clock inputs of the phase discriminator, to the second inputs of the cat cerned connected inverted output time code counter or direct outputs of which are connected to. constants whose inputs are connected the outputs of the sensor constants, and outputs are the outputs of the phase discriminator device. 3. The device of pop.2, characterized in that the crushing elimination unit contains m shift units combined by address and clock inputs, the output of each block being connected to the information input of the subsequent shift unit and to the corresponding adder input, the output of which is the output of the elimination unit crushing, the information input of which is the information input of the first shear block.