SU1084798A1 - Device for calculating modulo n remainder for given number - Google Patents

Abstract

A DEVICE TO CALCULATE THE REMAIN ON A MODULE FROM A NUMBER, containing a modulo adder, that is, with the aim of reducing the amount of equipment, the modulo adder contains (TIN - 1) binary adders, where ni - modulus, the first binary adder contains (L «t - 1) bits (- the number of the controlled number), the size of each subsequent binary adder is one less than the size of the previous binary adder, the input of the first term of each h is first bit of the first binary adder

Description

The invention relates to computing and can be used to convolve numbers by. module. A device for allocating the remainder in a variable module is known, which contains the number and module registers, the number and module decoders, the switch and the encoder, and the disadvantage of this device is the large amount of switch and encoder hardware. The closest in technical essence is a converter of a binary code into a modular code containing a modulo adder, K encoders m bits (tT n, AND is the binary code resolution, K p) the input register, whose input is the device input, the inputs of the input register are connected to the inputs of the respective encoders, the outputs of the encoders are connected to the corresponding inputs of the modulo l2j modulator. The disadvantage of the converter is significant hardware costs for implementing the encoders for a variable value of the module. The purpose of the invention is to reduce the volume of equipment. The goal is achieved by the fact that in a device for calculating the modulo residue of a number containing a modulo adder, the modulo adder contains (JYi - t) binary adders, where t is the modulus size and the first binary adder contains (, + ryi - 1) bits (P the size of the controlled number), the size of each post-secondary two & egg accumulator is one less than the size of the previous binary adder, the input of the first term of each i-th bit of the first binary adder (O i: And - 2) connected to (i + 1) -th bit controlled, numbers, the input of the first term of each j-th bit (h - 14 i M + m - 2) of the first binary adder is connected to the zero signal bus, the input of the first term of each k-th bit of the second binary adder (I Kfcim- 1, + + ГЯ Р) is connected to the output of the sum of (k + 1) -th bit (f - 1) -th binary adder, the first inputs of the second term of each binary adder are connected to the corresponding input of the module code of the device, transfer inputs each binary on the adder is connected to a single potential bus, the output of the sum of zero ra the p of each p-th binary adder (1 1) - 1) is connected to the second inputs of the second term, p - X bits of all binary adders, the output of the sum of each S-th digit of the last binary adder (, G) - 1) is connected to The second inputs of the second term (VY1 + 5 - 1) of the bits of the binary adders, the outputs of the sum (Hi - g) of the bits of the last binary adder (O 1 w - 1) are the output of the device. Due to the input logic in the circuit of the second term, the adders realize the function of binary subtraction, where the deductible is controlled by the value of the corresponding base code release. The implementation of this function and the organization of links to the scrapping of the inputs and outputs of the adders provides an algorithm for dividing the binary number by the base value, and the division is performed from the leading bits to the higher bits. The following notation is taken: And the original number; p - module Al Od - respectively, the integral part and the remainder of division, by p, the number A is the result of the specified integer division algorithm and is defined by the expression - O (p -) A A. where (f (p) is the Euler function of the base k is a positive integer whose value is determined by the length of the algorithm.In binary terms, when the initial number A is wider, the value of the digits of number A from Nth and older are determined only by the values (the values of the second term of expression in (1). bits modulate a group of m consecutive bits of the second-slot code It uniquely identifies the remainder and can be used to organize modularities. When the algorithm is limited by the size (+ m in bits from the nth to n + nk, the remainder is formed, coded by a group of m consecutive bits of the binary base element Ca, having the form - 1 (p -OC) R (ot) The drawing shows a functional diagram of a device designed to calculate the four successive bits of the code R (o (,) on any odd 4-bit modulus from a 12-bit one binary number. Standard identification is used to identify logic elements. The device contains binary summs 1 - 3 and adder 4 modulo. Input and output values are assumed to be binary-coded and are denoted: initial binary number ... module, with the lowest bit of the module being assumed to be always single (PQ 1). Residue code r,} Г fj, The circuit uses single-digit adders with input logic in the circuit of the second term. The input logic provides the execution of the Schaeffer dash logic function of other variables. One-bit adders are connected to three binary adders: the first is a 15-bit, the second is a 14-bit, and the third is 13 days. Due to the inversion in the logic function and the signal transfer to the zero bit, each of the adders realizes

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The proposed device allows the use of its post,

It is the same type, elements and provides significant savings in equipment compared to the prototype. There is a binary subtraction function. The first addend is decremented for the first adder, the sum of the output of the first one, the first adder for the second, the third adder, for the third is the value of the total output, starting with the first one, second adder. A subtractive is a binary value determined by the logical multiplication of two variables. The first variable is the value of the bits of the binary number, where the value of the zero bit is a., The value of the first bit is equal to I the value of the zero output of the first adder, the value of the second bit is equal to the value of the zero output of the second poro adder the values of the outputs of the third adder, starting with a zero bit. The second variable is the value of the code bits of the module, the value of p for the first adder, Py for the second, and P. the third for device operation. The device consists in calculating the difference between the first adder and the subtracted all three adders, The bits of the subtractable are determined by the implementation of the subtract function in the lower bits. The designation a, the value of the first variable of the subtracted, where i - corresponds to the numbering of the links according to the functional scheme, the operation algorithm has the form

Claims (1)

DEVICE FOR CALCULATING THE RESIDUAL MODULE FROM THE NUMBER, containing a modulo adder, characterized in that, in order to reduce the amount of equipment, the modulo adder contains (Ty - 1) binary adders, where u is the bit capacity of the module, and the first binary adder contains (, rb + n - 1) bits (in - bit number controlled), each successive bit binary adder at one less than the bit preceding binary adder, ^one input of the first term per- each h -th bit of the first binary adder (04ΐί η '-2) coupled with (i + 1) th discharge controlled number ^1, the input of the first term each -th bit (n - j 14 4 η + u - 2) of the first _dvoim-; of the adder connected to the zero signal bus, the input of the first term of each kth digit of the ith binary adder (K C <n - 1, 0 ^έ ki n + η) -β) is connected to the output of the sum of (k + 1) the discharge of the (E -1) -th binary adder, the first inputs of the second term of each binary adder are connected to the corresponding bits of the code input of the device module, the transfer inputs of each binary adder are connected to the unit potential bus, the output of the zero-bit sum of each r-th binary adder (16р <And -1) is connected to the second inputs of the second term p - x bits of the binary adders, the sum output of each serial binary adder ^ -th bit (B 1 <η - 1) are connected to the second inputs of the second term (+ 5 - 1) bits of all binary adders, the outputs of the sum of (, n -J *) -th bits of the last binary adder (0 4 Л 4 w ~ - - 1) are the output of the device / SU _n „1084798