SU1043620A1 - Device for input data into computer - Google Patents

Abstract

A DEVICE FOR ENTERING INFORMATION IN A COMPUTER, comprising a first control unit, the input of which is the synchronization input of the device and connected to the counter input and the synchronization of the reg-ister shift, the information input of which is the information input of the device, and the first and second outputs are connected to the inputs the buffer information register and the buffer register of service signals, respectively, the output of the first control unit is connected to the reset input of the counter, the output of which is connected to the first input of the second control unit and whose second input, the first input multiplexer and the control input of the memory block are the control input of the device, the first output of the multiplexer is connected to the address input of the memory block, the first information output p is connected to the third input of the second control unit, the first and the second one. The outputs of which are connected to the synchronization inputs of the buffer registers of information and service signals, respectively, the output of the buffer register of service signals is connected to the second input of the multiplexer, which is m, in order to increase the speed of the device in it. entered the interface block, the comparison block, the address and information key blocks, the first inputs of the comparison block and the information key block are connected to the output of the information buffer register, the second input; the information key block is connected to the output of the buffer register of service signals, the output of the information key block is connected to the information input of the memory block, the information @ input information input — you (I am the device stroke, and with the second input of the comparison block, the output of which is connected to the first control input of the unit) Nor, the second control input of which is connected to the third output of the second control unit, the first output of the interface block is connected to the control input of the information key block, the fourth 4, the input of which is connected to the bus of the EPS of the power supply point, the second output unit. It is connected to the control input of the lazy address block block, another input of which is connected to the additional output of the memory block, the output of the address key block is connected to the address of the multiplexer, which is the address input - output -. home device, the third exit block. The interface is the control input to the device output.

Description

The invention relates to computing, in particular, to input devices for information in a digital computer, and can be used to enter discrete information in IIBM. A device for inputting information into a digital computer is known, comprising a counter, a counter control unit, an input block, a shift register, an slab signal unit, a zone formation unit, a synchronization unit, a control unit, a buffer register with their connections 1. . The disadvantage of the device is low speed. . . Closest to the invention of the technical essence and achievable. The result is a computer input device containing a shift register, an information buffer register, an auxiliary signal buffer register, a counter, a counter control block, a read control block, a multiplexer, and a memory block. The first inputs of the counter, the shift register and the input of the counter control unit are combined and are the first input of the device, the second input of the shift register is the second input of the device, the first input of the multiplexer is the third input of the device, the first control input of the memory and the second input of the multiplexer are combined and, in. the fourth-input device, the second input block. the memory is the fifth input of the device. The multiplexer output is connected to the third memory input, the output of the meter control unit is connected to the second input of the counter, the output of which is connected, to the second input. read control unit, the third input of which is co, is the same as the output of the memory block. The first output of the shift register is connected to the first input of the buffer register. The second input of which is connected to the first output of the control unit by clearing, the second output of the shift register is connected to. the first input of the buffer register of service signals | The second input of which is connected to the second output of the read control block. The output of the buffer information register is the first output of the device, the output of the buffer register of service signals is connected to the third input of the multiplexer and combined with the second output of the device, the third output of the read control block is the third output of the device. , In the device, the indications of the need to receive in the digital computer input to the device are recorded in advance at the memory block. information input is selected information that is not programmed, is not accepted, information is needed is sent to CMV 2. The disadvantage of the known device is low speed, because the digital computer often re-informs the information, not carrying, in itself the novelty, i.e. The information of the current input session is identical to that of the previous session. It is useless to process this information. process time of a digital computer. The purpose of the invention is to increase the speed of the device. This goal is achieved by the fact that a device for entering information into a computer, comprising a first control unit, the input of which is the synchronization input of the device and is connected to the input of the counter and the syncro. the input of the shift register, the information input of which is the information input of the device, and the first and second outputs are connected to the inputs of the buffer information register and the buffer register of service signals, respectively, the output of the first control unit is connected to the reset input of the counter, the output of which is In the first input of the second control unit, the second. the input of which, the first input of the multiplexer and the control input of the memory block are the control input of the device, the first output of the multiplexer is connected to the address of the memory block, the first information output of which is connected to the third input of the second control unit, the first and second outputs of which are connected to the synchronization inputs of the buffer registers of information and service signals, respectively, the output of the buffer register of service signals is connected to the second input of the multiplexer, the interface block is entered, the block is compared ,, the blocks of address and information keys, the first inputs of the comparison block and the information key block are connected to the output of the information buffer register, the second input of the block, the information key, is connected to the output of the buffer register of service signals, the output of the information key block is connected to the information input the memory unit:; and, the information input of the device, and with the second input of the comparison unit, the output of which is connected to the first control input of the interface unit, the second control input of which is connected It is connected with the third output of the second control unit, the first output of the bobble block is connected to the third control input of the information key block, the fourth input of which is connected to the power supply bus. the second output of the interface unit is connected to the control input of the address key block, another input of which is connected to the auxiliary output of the memory block, the output of the address key block is connected to the multiplexer address input, which is the address input - device output, the third output of the interface block is The control input is the output of the device. Fig. 1 shows a c-structured electrical circuit of the device; in fig. 2 is a diagram of the first block of art; in fig. 3 is a diagram of a second control unit; in FIG. 4 is an interface block diagram. The device contains the first control unit 1, the counter 2, the shift register 3, the buffer information register 4, the buffer register 5 of the available signals, the second control block b, multiplexer 7, memory block 8, address keys block 9, block 10 information keys- , comparison unit 11, interface block 12, synchronization input 13, information input 14, address input 15 of the device controlling the device output 16 of the device, information input of the device output 17, reset input 18 of the counter input of the buffer register information 19, input -20 buffer register service signals 20, the address input 21 of the memory block, the first information output 22 of the memory block, the additional information output 23 of the memory block, the output 24 of the counter, the input 25 synchronizing the buffer register of the information, the input 26 synchronizing the buffer register of the service bridges: g of signals, output 21 of the buffer information register, output 28 of the buffer register of service signals, the second control input 29.. of the interface unit, the first control input 30 of the interface unit, the input 31 of the control unit of information keys ,, the input 32 of the control unit address block key, control input - output, 33 devices, another counter. 34 and generator 35 clock pulses, decryptor 36 and first element I 37, trigger 38 of signal Inquiry, trigger 39 signal a Zanto, trigger 40 signal Write - Read, logical element OR 41, the second element. And 42. .... . Information symbols are transmitted at a rate of (1 / T) baud. The iformacconna parcel begins with the omission, represented by K symbols. There are no synsempulses on the skip interval. Then, at the input 14, there are w service symbols, with the help of which the number of the information parcel is encoded. The h characters following them carry the immediate information content. Service and information symbols are accompanied by clock pulses at input 13. The device operates in two modes, -in the first mode, the control information in the memory of the input device is recorded in the first mode: one bit is a sign of the need to receive the information package, the remaining bits are they are the address of the memory of the digital computer on which it is necessary to receive the information parcel. Bit depth the part is determined by the size of the ad hoc space of the memory of the digital computer. The b i th cell 8 of the memory of the input device records control information for the information packet with the number i. The size of the information package number hi. -. -. Thus, the memory block 8 consists of 2 cells of the size (e +1). In the second mode, the information parcel is directly received into the device, the analysis of the need to receive this information parcel according to the sign of necessity, recorded in the first mode in memory block 8 and the analysis of the received information, but also in the event that the information of the current input session is not equal to the information of the previous input session, i.e. is a new, entry of this information with a bit of novelty in the memory. Digital computer at the address specified in the first mode of operation of the device. If; the information is not new, its recording in the memory of the digital computer is not made: Processor processes only the information in which there is a bit of novelty. . In the first mode, the device operates as follows. . . , By control signal 16 (logic level J ch mufflex 7 multiplies input-output 15 connected to the address bus of the digital computer; to address input 21 of the memory block 8; BLOCK 8 of the memory operates in the Record mode, via the information bus 17 of the digital computer The information input of the memory block 8. The processor receives the control information. -TaKjiM, by recording control information for all numbers of informational messages in the memory block 8. The device’s second mode is characterized by a logic level input 16. For this reason In the memory unit 8, the memory switch switches to the | | read mode, multiplexer 7 switches the output 28 to the input 21,.

During the pause (the interval for the passage of incoming information), the control unit 1 generates reset pulses for counter 2. The reset inputs of the counter 34 receive synchronizing impulses from the input 13 of the device. The generator 35 generates clock pulses for the counter 34 with the frequency f, several times excelling the input clock of the clock pulses at input 13. Thus, during the pause time, the counter 34 has time to at least reach the state when a logical unit appears at its output, zeroed counter 2.

 After the end of the skip interval, when sync pulses appear, the input 13 of the information at input 14,

starts to fill, shift register 3, and counter 2 starts counting the number of characters received.

The code from counter 2 enters at exit 24 to control block b .... Once m is received, the usolov

: on the output code of the counter 2, the control unit 6 is triggered. At its output, a write pulse appears, rising at input 26, according to which the information from input 20 of shift register .3 is written into buffer register 5 of service signals. Similarly, when p information bits arrive at the 3-shift register, a write pulse arriving at input 25 is formed in the control block b. In the buffer register 4, information is generated.

Thus, at output 27, the M-digit code of the received information appears, and at output 28, the MI-discharge code of the received parcel number. The multiplexer 7 commutes the code of the received parcel number (output 28) to the address input 21 of block 8 memory

The control information is read for the received information. It is sent from the memory block 8.

The sign of the need to receive this information package on output 22 enters the control unit b. If a

In the first mode of operation of the device, the indication of necessity is fixed in memory block 8, then a signal is generated at input 29, which is fed to mating unit 12. Block 12 mates occupies the trunk of the digital computer, a signal is generated at the input 32, which opens the keys of block 9, through which from block 8 to the address highway through the input - output 15 enters the address of this information parcel. and organizes reading from the memory of the DVM.information received in the previous report. input.

This information on the data bus of the digital computer is fed to the on-turn output of the device 17 and the input of the comparator unit 11. At the second input of the comparator unit 11, output information 27 is supplied from output buffer register 27. If the incoming information is not new, then at the output of the comparison unit 11 a comparison signal is generated which is available at the input / 30 (level of a logical unit), according to which the conjugation unit 12 resets - a signal at the input 32, opening the keys of the block 9, resets the capture signals of the highway DVR, and thus, the incoming information package is not recorded in the memory TS.VM.

If the newly received information is new, the output of the comparison unit 11 produces a non-comparison signal (logical level zero), according to which the interface unit 12 generates a signal opening the keys of the unit 10, and - organizes the recording in the memory Information CVM. With a novelty concrived bit. The novelty bit is formed by connecting to the auxiliary input of a 10-key voltage block +9 V (logic unit level J. Novelty bit-VO of the entered information is cleared at the end of processing by its processor. On the data line of the digital computer through the keys of block 10 supplies information outputs 27 and 28, and the address highway is fed through block 9 to the address of the memory of the digital computer from the output of memory block 8. After writing to the memory of the digital computer, the interface unit 12 resets the signals at inputs 31 and 32 of the key management of blocks 10 and 9 and the signals of the highway capture .

The signal at the input 29 from the control block b on the trigger 38 sets the level of the logical unit (.A signal), the trigger 40 sets the level of the logic one. on the control bus of the digital computer on input to output 33. The signal resolution (RZR) from the control bus on the digital computer on the trigger 38 is set to the level. logical zero (the signal is reset. DAD), on the trigger 39 is set-. The level of the logical unit (the signal ZAN is formed), which, via INPUT 32, is fed to the control input of the block 9 of keys.

By a single signal at input 30 from the comparison circuit (the incoming information does not carry any novelty), the flip-flop 39 is set to the logical zero state (the ZAN signals and the control signal at the input are reset. 32).

The zero signal at input 30 from the comparison circuit (a new information is supplied) at the output of the PI 42 generates a signal that goes to the control input of block 10 and sets the logic zero level at the output of the trigger 40 (the LAP signal). There is a recording of receipt information in the memory of the digital computer.

The signals at inputs 31 and 32 and the ZAN are reset by the Received response signal from the control bus of the digital computer after recording to the digital computer memory. The address and information received via blocks 9 and 10 on the trunk of a digital computer are accompanied by cavitating signals, which are omitted in the description of block 12.

Thus, in the input device, the incoming information is analyzed for ns viscosity by comparing the information of the current and previous input sessions. In the memory of a digital computer, only new information is recorded, and a bit of novelty is formed to it. Each informational parcel corresponds to a specific cell or memory area, the address of which is recorded in memory block 8, i.e. at the same time as the information is entered, it is sorted. As a result, an increase in speed is achieved, since the digital computer processor is not distracted by the sorting of incoming information, as well as by processing information that is not carrying cost.

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Claims (1)

A DEVICE FOR INPUTING INFORMATION TO A COMPUTER, comprising, a first control unit, the input of which is the synchronization input of the device. and connected to the counter input and the clock input of the shift register, the information input of which is the information input of the device, and the first and second outputs are connected to the inputs of the buffer register of information and the buffer register of service signals, respectively, the output is per. The first control unit is connected to the reset input of the counter, the output of which is connected to the first input of the second control unit, the second input of which, the first input of the multiplexer and the control input of the memory unit are the control input of the device, the first output of the multiplexer is connected to the address input. a memory unit, the first information output of which is connected to the third. the input of the second control unit, the first and second. the outputs of which are connected to the synchronizing inputs of the buffer registers of information and service signals, respectively, the output of the buffer register of service signals is connected to the second input of the multiplexer, characterized in that, in order to increase the speed of the device, the interface unit, the comparison unit, the address and information key blocks, the first inputs of the comparison unit and the information key block are connected to the output of the information buffer register, the second input block and the information keys are connected to the output of the buffer register of service signals, the output of the information key block is connected to the information input of the memory block, which is the information input - the output of the device, and to the second input of the comparison unit, the output of which is connected to the first control input of the interface unit, the second control input which is connected to a third output of the second control unit, the first output interface _unit: connected to the control input of the key information, the fourth input of which is connected to the power source bus, the second output of the interface unit is connected to the control input of the address key block, the other input of which is connected to the additional output of the memory block, the output of the address key block is connected. with the address input of the multiplexer, I being the address input - output -. the device’s house, the third output of the interface unit is the control input. - the output of the device. O.SU, 1043620, 1043620