SU1022169A2 - Device for automatic testing of random numbers generator - Google Patents

Abstract

DEVICE FOR AUTOMATIC MONITORING OF A GENERATOR RANDOM. NUMBER ON AUTH. St. No. 744608, characterized in that, in order to improve the quality control of multi-bit random number generators by calculating an estimate of the mutual correlation of the bits of the generated numbers, it further comprises sixth, seventh and eighth counters, thirteenth, fourteenth, fifteenth, sixteenth and the seventeenth elements And, the sixth and seventh switches, the tenth, eleventh and twelfth elements OR, the fifth trigger and the display element, and the inputs of the thirteenth element And connected to the outputs of the random generator and, sat, and the output is to the counting input of the sixth counter whose setup input is connected to the output of the fourth element OR, and the corresponding outputs are connected to the inputs of the sixth and seventh switches, the outputs of which are connected respectively to the inputs of the fourteenth and fifteenth elements And, the outputs of which are connected to the inputs of the tenth OR element, the output of which is connected to the first input of the fifth trigger, the second input of which is connected to the corresponding output of the control unit and the output of the second delay element, the first output The fifth trigger is connected to the first input of the sixteenth element I, the output of which is connected to the first input, to the eleventh element OR, the second output of the fifth trigger sub S is connected to the first input of the seventeenth element And, the second input of which is connected to the second input of the sixteenth element And to the output of the second driver and the output to the counting inputs of the seventh and eighth counters, the setup input of the seventh counter is connected to the output of the eleventh element OR, the second input of which is connected to the corresponding input of the control unit Control, the corresponding output of which is connected to the setup input of the eighth counter, the output of which is connected to the first input of the twelfth OR element, the second input of which is connected to the output of the seventh counter, and the output to the third input of the ninth OR element and the input of the indi element: - nation.

Description

I. The invention relates to computing technology and can be used in digital test instruments, automatic control devices, digital computers, in particular, in the statistical analysis of a multi-bit random number generator with a uniform distribution law. According to the main author. The device for automatic control of a random number generator containing a control unit is known; a random number generator whose outputs are connected to the first inputs of the first AND elements, the outputs of which are connected to the inputs of the first element OR, the output of which is connected to the first input of the second element And, to the input of the first delay element, the first counter, the second counter, the outputs of which are connected to the inputs of the decoder, the outputs of which are connected to the corresponding inputs of the first elements And, the third counter, the first input The first and second inputs of which are connected to the outputs of the third and fourth elements AND, respectively, the first input of the fourth element AND connected to the first input of the fifth AND element, the output of which is connected to the first input of the third element OR, the output of which connected to the second input of the third counter, and the second input of the third element OR to the output of the control unit whose corresponding output is connected to the primary input of the fourth element AND the output of which is connected to the first input of the the second input of the fourth element OR to the first input of the first trigger, the first input of the second trigger and the output of the second delay element, the output of which is connected to the first input of the third And element and the first input of the fourth And element, the second input of which is connected to the first the output of the first trigger, the second output of which is connected to the second input of the fifth element I, the third input of which is connected to the first output of the second trigger, the second output of which is connected to the second input of the third element of its element And, the fourth counter, the first input of which is connected to the input 1692 of the random number generator and the output of the sixth element I, the first input of which is connected to the output of the pulse generator, the outputs of the fourth counter are connected to the inputs of the fifth switch, the output of which is connected to the input of the second driver, the output of which is connected to the input of the second the delay element, the output of the fifth element I is connected. To the first input of the third trigger, the second input of which is connected to the corresponding output of the control unit, and the first output of the third trigger to the input of the first an actuator connected by its output to the input of the second counter, the second input of the second element AND and the control inputs of the eighth and seventh elements AND, the information inputs of the seventh element AND are connected to the outputs of the fourth switch, the outputs of which are connected to the first group of outputs of the first counter, the second group of outputs of which podu Yuchena to the inputs of the second switch. PN, the outputs of which are connected to the Information inputs of the eighth element And ,, exit. Which is connected to the first input of the first element of the OR, connected by the output to the second input of the second trigger, and the second input to the output of the ninth AND element, the control input of which is connected; Chen to the second output of the third trigger and The output of which is connected to the first input of the sixth OR element, the second input of which is connected to the output of the second element AND, and the output of the sixth element OR to the second input of the first counter, the third group of outputs of which is connected to the inputs of the nefciBoro switch, the outputs of which It is connected to the information inputs of the ninth element And, the fourth group of outputs of the first counter is connected to the inputs of the third switch, the outputs of which are connected to the information inputs of one-eleven. of the AND element, the control input of which is under (spun to the second output of the third trigger, and the output of the eleventh element AND to the first input of the eighth OR element, the output of which is connected to the second input of the first trigger, and the second input of the eighth element OR to the seventh And, informational inputs of the display unit are connected to 3 corresponding outputs of the decoder and the control input of the display unit to the output of the seventh OR element, connected by its first input to the output of the third counter, to the first input of the nine LI, the second input of which is connected to the corresponding output of the control unit, and the output of the ninth element OR to the first input of the fourth trigger, the output of which is connected to the second input of the sixth element I and the second input of the fourth trigger to the corresponding input of the control unit, the corresponding outputs which are connected to the second inputs of the group of meters whose outputs are connected to the inputs of the group of the seventh element OR, and the first inputs of the group of meters are connected to the outputs of the group of elements I, the first of which are combined and connected s to the output of the second OR gate, and the second group of elements moves you and connected to the corresponding outputs deshif torus, the second input of the tenth AND gate is connected to the input of the first delay element whose output is connected to the third input of the AND ten tog lj. Such a device makes it possible to perform quality control of random binary DF 11FRs formed in each discharge of a multi-bit generator, according to the magnitude of the mathematical expectation of the probability of occurrence of a logical unit (zero) and covariance 3. Discharge. However, it is not possible for emt to control the relationship between bits in the generated numbers, while the mutual correlation coefficient is equal to one (the known device will confirm the high statistical characteristics of the core generator, which is unacceptable). The purpose of the invention is to improve the quality of the monitoring performed by calculating the estimate of the mutual correlation of the values of the bits of the generated numbers. The goal is achieved by the fact that the device according to auth. If / TSBBOV additionally introduced the sixth, seventh and eighth counters, the thirteenth, fourteenth, fifth, sixteenth and seventeenth elements AND, the sixth and seventh switches, the tenth, one and ninth and twelfth elements OR, the fifth trigger and display element, and the inputs of the thirteenth element are connected to the outputs of the random number generator, and the output is connected to the counting input of the sixth counter, the setup input of which is connected to the output of the fourth element OR, and the corresponding outputs are connected to the inputs of the sixth and seventh intersection switches, the outputs of which are connected respectively to the inputs of the fourteenth and fifteenth elements AND, the outputs of which are connected to the inputs of the tenth OR element, the output of which is connected to the first input of the fifth trigger, the second input of which is connected to the corresponding output of the control unit and the output of the second delay element , the first output of the fifth trigger is connected to the first input of the sixteenth, the AND element, the output of which is connected to the first input of the eleventh element OR, the second output of the fifth trigger is connected to the first input One of the seventeenth: the element And, the second entrance of which. connected to the second input of the sixteenth element And to the output of the second driver, and the output to the counting inputs of the seventh and eighth counters, the installation input of the seventh counter-. The pin is connected to the output of the eleventh OR element, the second input of which is connected to the corresponding input of the control unit, the corresponding output of which is connected to the installation input of the eighth counter, the output of which is connected to the first input of the twelfth element ORI; second input of which is connected to the output of the seventh counter, and the output is to the third input of the nineth OR element and the input of the display element. FIG. 1 shows a block diagram of the proposed device; in fig. 2 - control unit; The device contains a control unit 1, a generator of 2 random numbers, a generator of 3 pulses, the ninth element OR 4, the fourth trigger 5, the first elements AND 6, the first element OR 7, the first delay element 8, the sixth element OR 12, the fourth counter 13, the fifth switch k, second driver 15, first counter 16, First - fourth switches 17-20, ninth, seventh, tenth and eighth elements And 21-2, eighth, fifth and fourth elements And, the second element 28 of the delay, the first and second triggers 29 and 30, third-fifth elements AND 31-33, second element OR s third ce snip 35, the third OR gate 36, the twelfth AND gates 37, n t1e counters 38, the seventh OR gate 39, indicating block 0, a third flip-flop il, first shaper k2, 3 a second counter, decoder, sixth to eighth counters. the thirteenth to seventeenth elements AND 48-52, the sixth, seventh switches 53 and 5, the tenth - the twelfth elements OR 55-57, the fifth trigger 58, the element 59 display. In this case, the generator outputs 2 random numbers are connected to the first in the heads of the corresponding elements AND 6, the outputs of which are connected to the inputs of the first element OR 7, the output of which is connected to the first inputs of the elements .and 10 and 11 and to the input of the first delay element 8 It is connected to the input of the element T1, whose output is connected to the first input of the element OR 12, the second input is connected to the output of the second element 10, and the output to. the first input of the first counter 16, the corresponding outputs of which are connected to the inputs of the switches 1720, the corresponding outputs of which are connected to the corresponding inputs of the And 21-2 elements, respectively, the outputs of the And 21 and 22 elements are connected to the first and second inputs of the element, OR 25, the output of which connected to the first input of the first trigger 29, the second input of which is under; connected to the output of the second delay element 28 {, the first input of the second three 30 and the first input of the fourth. the OR element 27, whose output is connected to the second input of the first counter 16, and the second input to the output of the control unit 1 (connection to simplify the drawing is not shown), the corresponding output of which is connected to the first input of the ninth OR element, the second input which is connected to the output of the OR element 39 and the first input of the display unit 0, the remaining inputs of which are connected to the second inputs of the corresponding elements 6 and 37 and the corresponding outputs of the decoder 4 via corresponding connections (a, b, ..., c) whose inputs are connected to the output The second counter, the first input of which is connected to the control unit 1, and the second to the output of the first shaper k2, the input of which is connected to the second input of the second element 10 and the first output of the third trigger A1, the second input of which is connected trigger input k is connected to control unit 1, and the second input to the first input of the OR 36 element and the output of the AND 33 element, the first E) stroke of which is connected to the first output of the trigger 30, the second input to the first output of the trigger 29, the second output of which is connected to the first input element. And 31, the output of which is connected to the first input of the element. OR 3, the second input of which is connected to the output of the element AND 32, and the output to the first inputs of the elements AND 37 and the first, the input of the third counter 35, the second input of which is connected to the output of the element ZB OR, and the output to the first input of the element OR 39, The remaining inputs of which are connected to the outputs of the corresponding counters 38, the first inputs of which are connected to the outputs of the respective elements AND 37 and the first inputs of the third counter 35, the second input of which is connected to the output of the element OR 36, and the output to the first input of the element OR 39, the remaining inputs which under The switches are. To the outputs of the corresponding counters 38, the first. whose inputs are connected to the outputs of the corresponding AND 37 elements, and the second inputs to the control unit 1, the corresponding output of which is connected to the first input of the Fourth trigger 5, the second input of which is connected to the output of the ninth OR element, and the output to the first input of the AND 9 element, The second input of which is connected to the generator output 3 pulses, and the output to the generator input 2 random numbers and the first input of the counter 13, the second input of which is connected to block 1, and the outputs to the inputs of the fifth switch H, the output of which is connected via the second f distributor 15 to BXO;: Q of the second delay element 8, the second input of the element 31, the third input of the AND 33 element and the first input of the AND 32 element, the second input of which is connected to the second output of the trigger 30, the second input of which is connected to the output of the OR 26 element The inputs of which are connected to the outputs of the And 23 and 2k elements, the inputs of the thirteenth element And kB are connected to the outputs of the generator 2 random numbers, and the output to the first input of the sixth counter L5, the second input of which is connected to the output of the fourth .OR.2.2, and the corresponding outputs are to the inputs of the sixth 53 and the seventh 5 switches, the outputs of which are connected to the inputs of the fourteenth 49 and fifteenth 50 elements AND, respectively, the outputs of which are connected to the inputs of the tenth element OR 55, the output of which is connected to the first input of the fifth trigger 58, the second and third inputs of which are connected to the corresponding the output of the control unit 1 and the output of the second delay element 28, the first output of the fifth flip-flop 58 is connected to the first, the input of the sixteenth AND element 51, the output of which is connected to the first input of the eleventh element OR 5b, and the second output The second trigger is connected to the first input of the seventeenth element I 52, the second input of which is connected to the second input of the sixteenth element I 51 and to the output of the second driver 15, and the output to the first inputs of the seventh 46 and eighth 47 counters, the second input of the seventh counter is connected to the output of the eleventh element OR 56, the second input connected to the corresponding output of the control unit 1, the corresponding output of which is connected to the second input of the eighth counter 47, the output of which is connected to the first input of the twelfth element OR 57, second second input of which is connected to the output of the seventh counter 46, and the output - to the third input of the ninth OR gate 4 and the input display element 59. The elements 1-44 function in full accordance with the prototype. The introduced elements 45-59 are designed to calculate the values of the correlation estimate between the rows. The calculation of this estimate is carried out automatically and in parallel in time with the calculation of estimates of the mathematical expectation of the probability of occurrence of a logical unit (zero) and covariance in bits. The introduction of new blocks and connections is not reflected in the structure of the control unit of laziness and its operation. Various specific implementations of control unit 1 are possible; however, in the simplest case, control unit 1 can be represented by two buttons; When the first button is pressed, all elements of the device's memory are reset, and when the second button is pressed, a START signal is generated (Fig. 2). In the initial position, all the memory elements in the switches 13.1b, 35.38, L5 and 7 and the triggers 5,29,30.tl and 58 are in the zero position, the code corresponding to the number of the generator is set in the counter. 2 random numbers from which the monitoring of the multi-discharge generator 2 begins, By means of a switch 1, the output of one of the memory elements of the counter 1 3 is connected to the input of the driver 15, thus setting the duration N of one test cycle. By means of switches 18 and 20 to the inputs of the elements 22 and 24, the outputs of the corresponding memory elements from counter 16 are connected, so that when the code in counter 16 reaches the lower limit of permissible values P (X |), where P (x4) is the probability of occurrence of a food. (zero) in a controlled bit i-th the operation cycle of the device; A signal appears at the output of AND 24, and when it reaches the boundary P (x) jjjjnpo, there is a signal at the output of AND 22, if there is a permitting potential at the control inputs of the And 22 and 24 elements. The number of the memory elements of the counter 1b is determined by comparing the confidence interval and its code equivalents, i.e. is uniquely determined by the values of N and (degree of trust). By means of switches 17 and 19, the outputs of the corresponding memory elements of counter 16 are connected to the inputs of elements 21 and 23 so that, if there is a resolving potential at their control inputs and when the code reaches 16 values of P (x,) ;; Pfx-x- l where P (,,) is the probability of a joint event of the occurrence of units (zeros) in the controlled discharge in the i-th and i + v-th cycles of the device bots, -the signals on the outputs elements And 23 and 21 respectively. Moreover, the numbers of the selected elements of the memory counter 16

9

also uniquely defined by the values of N and a. By means of switches 53 and 5 to the inputs of the AND kS elements to 50, the outputs of the corresponding memory elements from counter 5 are connected, so that when the code in the kS counter reaches the lower limit of the permissible values P (.), Where P (xx / .., Xni ) - the probability of a joint occurrence of units (zeros) in all generator bits 2 is odonally (in the i-th cycle), a signal appears at the output of the element And 9, and when the upper limit P (.x) D is reached appears at the output of the element And 50. The numbers of the elements, the memory of the counter 5 are also determined by comparing the boundaries of the trust interval of and. its code equivalents,

When the START signal arrives at the first input of the fourth trigger 5, the latter is transferred to the single state, thereby allowing the 9 pulses from the oscillator 3 to pass through the AND 9 element. The pulses from the AND 9 element output go to the first (summing) output counter 13 and the input of a multi-dimensional generator of 2 random numbers. At the same time, the counter 13 counts each clock pulse coming from the element E.E. Pulses, arriving at the input of the generator 2, provide for the synchronous generation of multi-digit random numbers. The device is not critical to the implementation principles of the 2 random number generator, i.e. As such a generator, any of the known / other discharge generators can be used. Each bit of generator 2 is connected to the corresponding element AND of the group of elements AND 6, from the output of which the signals go to testing to calculate the values of the estimates P (x) and P (x.) V. In addition, each discharge of generator 2 is connected to the corresponding input of the element E D8, at the output of which a signal appears only if in a given cycle for j 1, 2, ..., t, where m is the generator size 2. The signals from the output of the element And In come to the first (summing input of the counter) A5. The decoder decrypts the state of counter 3. With one of

02216910

outputs (a, b, ..., c) of the decoder Q appears the resolving potential, which opens the corresponding elements And 6 and 37. Therefore,. random pulses generated by only one bit of the generator 2 are passed to the input and output of the element OR 7. Since the trigger k is in the zero position, the element 10 is open,

10 and element 11 is closed. Therefore, the signal from the output of the element OR 7 passes through the elements AND 10, OR 12 to the second input of the counter-.16, t, e. the counter 16 counts only those random pulses that are generated by the selected generator discharge 2. After the pulses are counted by the counter 13, the signal from the output of its selected memory element (trigger) passes through a switch

I to the input of the imaging unit 15, which forms a standard (for the selected element base) pulse, which is blunt to the corresponding inputs

25 elements And 31 and 32, the second inputs of the elements And 5t and the element 28 of the delay. Over the same time, n counts are accumulated on counter 16, and if

mirt

 P (x)

(one)

N aon

Those. the number in the counter 16 is less than the permissible limit, the signals do not appear on the element And 22, nor on the element 2, therefore the triggers 2930 remain in the initial zero position. Therefore, the signal coming from the driver 15 to the first input of the element And 32 passes through the element OR 3 to the first (summing) input of the counter 35 and the first inputs of the elements And 37. One of the elements And 37, corresponding to the selected generator bit 2, passes the specified signal to the summing input of the corresponding counter 38. This is recorded every single time the value goes beyond the lower permissible limit. Similarly, the outputs of the counter code 16 are fixed at the upper permissible limit, which occurs under the condition

  that ,, vWait APP P (x -)., „M

(2)

However, in this case, the triggers 29 and 30 before the arrival of the M-th pulse from the output of the element And 9 are transferred to one state by signals from the elements OR 25 and 26, respectively. The resolving potential from the single (second) output of the trigger 29 opens the element I 31, through which the inputs from the counters 35 and 3 pass through the signal from the output of the driver 15. If p-X, (3) auxiliary Aop J, then during the time of arrival of N clock pulses at the input counter 13 element And 2 will form a signal (at n) ,. which translates trigger 30 into a single state. In this case, the element 33 I turns out to be open on two inputs by the resolving potentials from the zero output of the trigger 29 and the single output of the trigger 30. The signal from the output of the imaging unit 15 through the AND 33 element enters the counting ((second) input of the trigger 41 and the first input of the element OR 36, the passage through which sets the counter 35 to the initial state, the same: the signal from the input of the shaper 15, having lingered on element 28, sets the trigger 29 and 30 and the counter 16 to the initial state. This completes one cycle of one bit test and the deviation from equal operation. The operation of the device in the next test cycle is determined by the fulfillment of one of the conditions (1), (2), (3) of the previous cycle. During this time, n pulses are accumulated on the counter 5, and if 4IWn „/, P (x , X2 ... Xm WN, Auxiliary Supplementary Ie, the code in counter 5 is less than the tolerance of my boundary, the signal at the output of the electrical element I 9, and consequently, at the output of the element OR 5 does not occur. Therefore, the trigger 5 & remains in zero: state. The high potential from the second (zero) output of this trigger keeps it open,. r-h element And 52. The signal coming from in, the stroke of the driver 15, passes through the element And 52 to the first (summing) inputs of counters 46 and 47. This fixes every single output value n for the lower acceptable limit. When the value of n exceeds the top of the scientific research institute, the permissible limit when 1a ".. gviiiM .. Vn P (l. Signals appear first at the output of the And 49 element, then And 50. These signals arrive at the first (counting) input of the trigger 58, which is first converted to the one state and then to zero. Consequently, the signal from the output of the imaging unit 15 also passes to the counters +6 and i., This is recorded every single time. For the upper limit, allow the output of the fifth limit value. If P P dop, then during the arrival time of N clock pulses at the input of the counter 13, And AE will form a signal when n). which translates trigger 58 into a single state. In this case, the AND 51 element is open for passing the signal from the output of the former 15 nd to the first input of the OR 5 element. This signal, passage through the OR 5b element,. enters the second input of the counter 4b and sets it to the initial state, after which the signal from the starting side of the delay element 28 sets the trigger 58 to the initial state. This concludes one generator test cycle for the presence of cross-correlation in the bits. Such test cycles are repeated until they register on the counter of 6 outputs for another range of the value of P (x; X2 ... Hgi) beyond the permissible limits, or p outputs for the entire test period on the counter. In these cases, the corresponding signals are generated either by the counter ii6 or by the counter 7, which pass through the element. ment OR 57, arrive at the display element 59 and through the OR element to the trigger 5. The signal from the output “5 blocks the passage through the element AND 9 clock pulses”. owls Device operation is terminated. If conditions (1) or (2) are satisfied in the previous cycle. Then the operation yct "/ i lauw.a y", the calculation of the corresponding - v, jrw evaluations on the counter 16 does not differ from the previous one up to the overflow of the counter 35. The signal from the switching of the counter 35 With it,,. the passage through the element OR 39 enters the block of the display and the second input of the element OR 4. The signal from the output of the element OR 4 sets the trigger 5 to the initial state, blocking the caMbiM clock passing through the element AND 9. The signal received at the first input of the block 40 indications, lights the indication of the number of the discharge that was analyzed before and came under suspicion of a malfunction. If condition (3) is fulfilled in the previous cycle, then in the following cycle, the test type on counter 1b is changed from equal to correlation and set. The difference between the modes of equal and correlated is that trigger 1 in the first mode elements 10 and 22 and 24 open up their resolving potential from the zero (first) output, and in the second mode the elements AND P, 21 and 23 are open. On the P element P, the instantaneous values of O AND 1 (random numbers generated in the i-th and i + v-th bars in the selected J-OM bit de gen. a 2, where v is the signal delay in element 8. Thus, in the correlation mode, the counter 16 receives random pulses, the essence of which is the probability of a joint event (x | x), i.e. The following conditions are checked: and -c II P (x, x, l iAon -t + V / AOn -Plx.x, mox ,, tiv / Aori nun, n Lop, and the output of the value n beyond permissible limits is recorded in the counters 35 and 38 (in one of the counters 38), finding the admissible within the admissible limits translates the scheme n 9 checking the uniformity of random binary digits jf of the 1st digit. So, when trigger 1 goes from one state to zero, the driver generates a pulse, which increases the count state by one. In the decoder:: LA, the next order of output is excited, which selects the next bit of generator 2. Thus, the introduction of new functional blocks and connections ensures the achievement of new quality: the possibility of automatic control of malfunctions of a multi-bit random number generator that leads to dependencies of values of random numbers in various bits. The device allows, by simple means, to calculate the estimates of all the main characteristics of the quality of the func- tioning of random number generators: the probability of the occurrence of random numbers in bits, their auto- and mutual correlation. The use of such devices eliminates the need for constant test checks with the help of EVM.The introduction of a random number generator supplied by an automatic control device will ensure economic benefits by increasing the performance of the random number generator, the labor of operators (maintenance personnel) and reducing machine operation. time spent on a significant number of test checks.

Claims (1)

DEVICE FOR AUTOMATIC CONTROL OF RANDOM GENERATOR. NUMBER by author St. N ° 744608, characterized in that, in order to improve the quality of control of multi-bit random number generators by calculating the mutual correlation of the values of the digits of the generated numbers, it additionally contains the sixth, seventh and eighth counters, the thirteenth, fourteenth, fifteenth, sixteenth and seventeenth elements , sixth and seventh switches, tenth, eleventh and twelfth OR elements, fifth trigger and indication element, the inputs of the thirteenth AND element connected to the outputs of the random chi generator, sat, and output - to the counting input of the sixth counter, the installation input of which is connected to the output of the fourth element OR, and the corresponding outputs are connected to the inputs of the sixth and seventh switches, the outputs of which are connected respectively to the inputs of the fourteenth and fifteenth elements AND, the outputs of which are connected to the inputs of the tenth OR element, the output of which is connected to the first input of the fifth trigger, the second input of which is connected to the corresponding output of the control unit and the output of the second delay element, the first output of the fifth trigger An era is connected to the first input of the sixteenth AND element, the output of which is connected to the first input, to the eleventh OR element, the second output of the fifth trigger is connected to the first input of the seventeenth AND element, the second input of which is connected to the second input of the sixteenth element Inc to the output of the second driver, and the output is to the counting inputs of the seventh and eighth counters, the installation input of the seventh counter is connected to the output of the eleventh element OR, the second input of which is connected to the corresponding input of the control unit, corresponding eighth counter whose output is connected to the installation entry, whose output is connected to the first input of the twelfth OR gate, the second input of which is connected to the output of the seventh counter, and the output - to the third input of the OR gate, and the ninth entry indicating element.