SU1020819A2 - Device for taking antilogarithms to the base two - Google Patents

Abstract

DEVICE FOR THE POTENTIAL OF LOGARIFMES AND THE BASIS TWO ON AV. Fe ZO4574, characterized in that, in order to increase the accuracy of potentials. nor, the summat is entered into it, with the input of the lower part of the integer part of the first operand adder connected to the input of the logical unit of the device, the input of the fractional part of the first operand sum: the torus is connected to the input of the code m (Tissa device, the input of the organization constant is connected to the input the second operand of the adder, the code of which is connected to the information input of the shift register.

Description

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/, {x 1 The invention is relative to the computing technique and can be used in the computational vocal techniques for potentiating the logarithms on the base two. According to ocHOBHOf.y auth. C., No. ZO4574, there is a device for potentiating logarithms on the base two, containing a clock generator, a characteristic register, a counter, a comparison circuit, an AND circuit and a shift register. The disadvantage of the device is a high computation of subarseness. The purpose of the invention is to improve the accuracy of potentiation. The goal is achieved by adding an adder to the device for potentiating the logarithms on the base of the cell, and the low-order input of the whole part of the first operand of the coolator is connected to the input of the logical unit of the device, the fractional part of the first totalizer position of the device is connected to the input of the device mantissa code, the device constant input connected to the input of the second operand of the adder, the output of which is connected to the information input of the shift register; FIG. 1 is a functional diagram of the device. The device contains a register of 1 characteristics, a counter 2, a circuit FROM, a circuit 4 of comparison, an adder 5, a register 6 of shift, a generator of 7 clock pulses. Figure 2 shows histograms of the distribution of the relative error of potentiation (a for the prototype, b for the proposed device). The operation of the device is based on an apn of the proximation of the function Y by 2 straight segments. The ashtroxing direct equation has the form (, 0625, where X is the BINARY logarithm P, the logarithm characteristic :, is the mantissa of the logarithm. It follows from the equation that, to determine the number Y by its binary logarithm, it is necessary to subtract the logarithm from the logarithm reduced by one, which corresponds to replacing the logarithm with the value of the obtained reduction decreasing the multiplied result by 2, which corresponds to a binary shift in the number of shifts by n times. In the initial state And the characteristics register 1 and the counter 2 are set to zero, the circuit. And the 3, controlled by the output signal of the comparison circuit 4, is open. The adder 5 operates in the reverse code. The number 1 + is fed to the inputs of the first cy operand, i.e. Rare d with weight 2 is supplied with a logical unit, and the number of mantissa is fed to the bits corresponding to the fractional part. The return code of the number 0.000100 a is fed to the inputs of the operand of the adder. On the adder 5, a constant 6 is generated, LLC . Obtained at the output of the adder 5, the number 1 O, is recorded characteristic of the logarithm. The clock generator 7 generates pulses coming through the open circuit AND 3 to the clock synchronization input of the shift register 6 and the counting input of counter 2. When n pulses are input, the number recorded in shift register 6 is shifted to the left by n bits, and the number at the output of counter 2 equal to the number recorded in register 1 characteristics. In this case the comparison circuit 4 is activated and locks the AND 3 circuit, preventing a further shift of the number in the shift register 6. Thus, the number entered into the shift register 6 is multiplied by 2 and fed to the output of the device. Relative error & calculated in accordance with the expression (-.0-0, With changes in X from O to 32 with O, O1). The average relative magnitude (Fig, 2) for prototype g is 4.1%, and for the proposed device wS 1, 6%. The technical and economic efficiency of the device being offered is that with minor additional hardware costs compared to the prototype (one adder), the relative error of the potentiator decreases by a factor of 2.6 by a factor of 0. 0 0.5 i f.5 g J 4J agg4 Ci224 0 0.5 / .52 2.6 J 3.5 4

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Claims (1)

DEVICE FOR POTENTIATING LOGARITHMS ON THE BASIS-, NII TWO by ed. St. No. 304574, characterized in that, for the purpose of increasing the accuracy of the potentiating. of input, the adder is inserted into it, and the input of the least significant part of the first operand - adder is connected to the input of the logical unit of the device, the input of the fractional part of the first operand of the adder is connected to the input of the device mantissa code, the input of the device constant is connected to the input of the second operand of the adder, the output of which is connected to the information input of the shift register. .SU., „1020819>