SU1019636A1 - Majority device - Google Patents

Abstract

MIZHITRITARNOGO..STROYSTVO, soda | In each of the three channels, a redundant block and a reversible counter, the outputs of the information bits of which through the first element OR are connected to the first input of the first element, and the second input of which is connected to the output of the digit discharge of the counter, and the output to the corresponding recovery unit, o t l and h ya e with the fact that, in order to improve the reliability of the device,. It contains in each WTO channel; ROA element OR, delay element, I element NOT and the second and third elements AND, the first inputs of which are connected to the output of the redundant unit, the output of the second element AND through the delay element connected to the first input of the second element OR whose second input is connected with the output of the third element And, the output of the second element OR is connected with the summation of the input of the counter, the subtractive input of which is connected with the output of restoring. livak tsego block, with vgaram the entrance of the second element AND through the element NOT - with the second entrance of the third element I. f sy 00 o:

Description

Exclusion refers to a car and a computing technique and can be used with. built digital devices of various names with increased demands on their reliability. An adaptive majoritarian device is known that contains control blocks, the inputs of which are connected to the outputs of redundant blocks, the corresponding information inputs and output of the restoring block, and adaptation blocks, the outputs of which are connected to the corresponding control inputs of the restoring block, and the inputs with equal the outputs of the control units, 1. The disadvantage of this device is that it becomes inoperative if the output signals of the redundant blocks are not synchronized with each other. It is also known a device for the majority choice: A signal signal containing input sources connected via an OR-NOT element and a delay element to the output blocks, which contain triggers and AND elements (2. The disadvantage of such a device is that it does not It allows malfunctions only when the input signal duration is equal to the value of the constant time of the secondary element. The closest in technical Essence of the invention is a prioritized device containing three reversible counters, outputs the formation bits of each of which are connected via the corresponding OR element to the first inputs of the corresponding AND element, the other input of which is connected to the output of the sign-discharged counter, the outputs of the AND elements are connected to the corresponding inputs of the restoring block, the output of which is connected to the subtracting inputs of the reverse meters 3 A disadvantage of the known device is the low reliability due to the failure of reversible meters in the case of simultaneous arrival of pulses on the summation and subtracting inputs Such a case is possible when the time delay for the signal components of the apparatus coincides with the time rassinhronieatsii adjacent channels. The purpose of the invention is to improve the reliability of the device by eliminating the simultaneous arrival of pulses on summation and subtracting the inputs of any of the three channels. This target is achieved by. that in each channel of the majority device, containing a reserved block, reversible card outputs of information bits of which through the first OR element are connected to the first input of the first element AND, the other input of which is connected to the output of the sign bit of the counter, and the output to the corresponding input of the recovery block, introduced the second element OR, the delay element, the element NOT and the second and third elements AND, the first inputs of which are connected to the output of the corresponding redundant block, the output of the SECOND element AND through The delay element is connected to the first input of the second element OR, the other input of which is connected to the output of the third element AND, the output of the second element OR is connected to the summing input of the reversible counter, the schlachitelny input which is connected to the output of the restoring block, to the VTO1YALM input of the second element AND and through the element NOT - with the second input of the third element And, the drawing shows the block diagram of the proposed majostandarngo device. The majority device contains redundant blocks 1, elements AND 2, elements 3 delays, elements NOT 4, third elements AND 5, then elements OR 6, reversible counters 7, first elements OR 8, first elements AND 9, restoring unit 10. Principle of device operation In the correct state, during a certain time during the synchronous operation of the reserved blocks, the output of the device passes a number of pulses equal to the number received from the blocks, and depending on the desynchronization options of the device's cutoff, equal to the number of units of two of the three Kangshov devices from the EC units reserved, or the average of the three number of pulses. Thus, the device majorizes the output signals of redundant blocks. The device works as follows. If the initial state of the reversible counters 7 is zero, and in the sign bits - units, which correspond to positive numbers, then at the same time they receive pulse signals from the reserved blocks 1 through the elements connected in series AND 5 and elements OR 6 arrive at the summing inputs of the counters 7 of the corresponding channels and in all counters a positive number is written: +1, the output of all AND 9 elements appears to be resolving levels and a signal appears at the output of the restoring block 10. This signal is received vyhssch majority device and subtracting inputs of all counters 7 / setting them in iskhs Noe state. At the same time, the number of pulses that are passed through the output of the device is equal to the pulsed output from redundant blocks 1. Possible cases of non-synchronous operation of the reserved blocks 1 can be considered in three variants: the first option is the output signal | redundant block 1 of two channels synchronized and the output signal of the reserved block i of the third kangsha races: synx i 1 {zirova11 is relative to them, while the drain times (McMKex & JTb roniection is more or less than the period after an interval of an impulse OBJBTO swarm output the signals reserved for e1 vlx of blocks 1 of all three channels were disassembled by an amount not exceeding the pulse following period; the output signals of redundant blocks 1 of all three kangshovs, coAepxcaiwie equal numbers of pulses, were scattered by an amount g I have several periods of impulse following. Ori The first variant of channel desynchronization device works in the following way. Hushes from the outputs of redundant blocks 1, works of synch sync but come through elements connected in series AND 5 and elements or b Hfi summing inputs of counters 7 and a 1 x 7 counter is written a positive number +1, AND 9 elements are opened and a signal appears at the output of the restoring block 10. This signal will go to the output of the majority device and to the subtracting inputs of all the counters 7, set two of them to the zero state, and in one will write a negative number of -1. If the channel desynchronization time does not exceed one pulse period, the pulse that occurred at the output of the unsynchronized reserved block 1 will pass to the summing input of counter 7 through AND 5 and OR 6 elements and set it to zero state until the next pulses appear at the outputs synchronized reserved blocks. In the case of coincidence of the moment of appearance of a pulse at the output ((asynonized redundant unit 1 with the moment of appearance of the pulse at the device output, the pulse setting the counter 7 of the out of sync channel to the zero state will go to its summing input through connected in series; you And 2, delay elements 3 and elements OR 6. When ets and if the delay time on element 3 is equal to the channel desynchronization time, then the counter 7 of the desynchronized channel will still be set to zero delayed pulse cm, since the impulse input to the test input is delayed by the propagation time / signal through counter 7, the element OR 8, and the recovery of block 10. The indicated time of the switch npeBfsuaeT to switch the counter 7 from state -1 to zero. If the channel desynchronization time exceeds one period of pulse tracing, the device works similarly to the case considered, but when it comes to the appearance of the first pulse at the output of the redundant synchronized channel unit 1 in counter 7, this will be the number -1 was found, since the same number of pulses worked from the outputs of the reserved blocks 1 of all three channels for one cycle, then at the end of the cycle of operation of the device all the counters are reset to the initial state.llpii of the first variant for a certain time, it is equal to the maximum voltage in the impulses received from the outputs of the reserved blocks working synchronously. In the second variant, the desynchronization of channels to the device works as follows. The impulse that appeared at the output of the reserved block 1 first will pass through the elements AND 5 and OR 6 and will be written into the corresponding output. counter 7, but it will pass to the output of the device only after a pulse is output at the output of the reserved unit 1 of another channel. After that, the output signal of the device, which appeared at the output of the recovery unit 10, will go to the subtractive inputs of the reversing counters 7 of all three channels and set two of them to the zero state, and one will record a negative number -1; If at the time of arrival of the subtracting inputs of the counters 7 at the output of one. : L of several reserved blocks 1 (there will be signals, they will pass

on the summation of the inputs of the counters 7 through the successively included elements AND 2, elements 3 delay and elements OR 6. The delay time of the signals on the element scs 3 delays is chosen by the longer duration of the signals from the reserved blocks 1 After the appearance of a pulse at the output of the reserved block of the third channel, a reversible counter 7 of this channel is also set to the zero state, but the output state of the device does not change.

If at the moment when a signal appears at the output of the device, a pulse appears at the output of the reserved third channel block, then this pulse passes to the summing input of counter 7 with a delay on element 3. At the same time, the delay time on element 3 will be equal to the desynchronization time of the reserved third block. the channel with the reserved block 1, the output signal of which causes the appearance of the signal at the device output, the reversible counter 7 of the third channel (as indicated above) will still be set to the zero state.

In the second version of the channel desynchronization, the number of pulses transmitted to the output of the device over a certain time is equal to the number of pulses received from the outputs of two of the three redundant units of the device.

In the third variant of channel desynchronization, the device operates as follows: hedgehog.

If pulses at the output of reserved blocks 1 appear successively in the first, second and third channels, respectively, by the time pulses appear at the output of the reserved block 1 of the second channel, the number + 1 will be recorded in the counter 7 of the first channel. Pulses from the output of the reserved Block 1 of the second channel is output to the output of the device and to the subtracting inputs of the 7 of all three channels. To the pulse occurrence at the output of the reserved block 1 of the third channel in the counter 7 of the first channel a number of at least +1 will be recorded, in the counter 7 of the third channel the number is less than -1, and the counter 7 of the second channel will be in its original state.

5 At the end of the cycle of operation of the device, determined by the maximum operation time of the reserved blocks 1 ,. counters 7 of all three channels are set to their original

0 state.

In the third variant of the out-of-sync channels for a certain time, the number of pulses will be received from the outputs of the reserved blocks 1, respectively, n, n, n,.

the output of the device will pass the number of pulses P2.

In the proposed majoritarian device for delaying pulses

Q coming from the output of the device to the summing inputs of the reversible meters 7, delay lines of the LZT type can be used. The wharf of the choice of a concrete type delay line should be made in order to exceed the delay time of the duration of the pulses from the reserved blocks. For example, with pulse duration, 0 ISS, as elements of 3 delays, lines can be used

h.Azerzhki LZT-4.0 - 1200 with a value of delay time t 4.0 μs.

Thus, as a result of the delay of signals arriving at

5 totalizing inputs of counters 7,

with respect to the signals arriving at their subtractive inputs, meter malfunctions are eliminated i, i.e. the majoritarian device works reliably when 0 is an arbitrary amount of out-of-sync signals from redundant blocks of adjacent channels. .

The technical and economic effect of the 5 uses of the invention lies in the fact that the device allows to reserve the equipment, whose operation is not synchronized with each other, no restrictions are imposed on the input signals, which in many cases allows simplifying redundant systems as a whole.

Claims (1)

MAJORITY .. DEVICE containing in each of the three channels a redundant unit and a reversible counter, the outputs of the information bits of which are connected through the first element OR to the first input of the first AND element, the second input of which is connected to the sign output of the counter, and the output to the corresponding input of the recovery unit, in that with the aim of increasing the reliability of the device, it contains in each channel a second OR element, a delay element, a NOT element and a second and third AND element, the first inputs which soi. are dined with the output of the corresponding reserved unit, the output of the second AND element through the delay element is connected to the first input of the second OR element, the second input of which is connected to the output of the third AND element, the output of the second OR element is connected to the totalizing input of the counter, subtracting the input “The horn is connected to the output of the recovery unit, with the second input of the second element AND through the element NOT — with the second input of the third element I.