SU1019616A1 - Time selector - Google Patents

Description

Rie. one

The invention relates to a pulse technique and cuff to be used, for example, in measuring devices.

Known time selector that contains the counter number of pulses, the decoder, the trigger, the output of which is connected to the input element And f 1 J,

The closest in technical essence to the present invention is a time selector containing an element I, the output of which is connected to the output bus of the device, the first input to the input bus of the device and the input of the pulse counter, the second input to the output of the trigger, and the decoder {, 2.

A disadvantage of known devices is low operational reliability.

The aim of the invention is to improve the reliability of the device.

The goal is achieved by those. that in the time selector containing the element I, the output of which is connected to the output bus of the device, the first input is with the input bus of the device and the input of the pulse counter, the second input is with the output of the trigger, the end setter of the pack end code, the start start code master, the second comparison elements of the codes, the outputs of which are connected respectively to the first and second inputs of the trigger, the first inputs are connected to the output of the pulse count, the second input of the first comparison code element is connected to the output of the start of the pack start code, the second the input of the second element of the comparison of codes is connected to the output of the setting unit of the end of the pack code.

Figure 1 shows the structural electrical circuit of the device; Fig. 2 shows diagrams explaining the operation of the circuit.

The device contains an AND 1 element, a trigger 2, a pulse counter 3, a dial start code setting device 4, a pack end code setting device 5, a code end comparison elements 6 and 7, input and output busbars 8 and 9.

The device works as follows.

Consider the operation of the device, for example, to extract the bursts from the k-th to the t-th pulses. At the same time, the code K-1 is set on the setpoint beginner code, and the code m is set on the end codesetter. The way of setting the codes is determined by the selected technical implementation of the setters. By the control command, the pulses of the input sequence arrive at the input bus 8 (Fig. 2a), and the counter 3 begins to fill.

On the trailing edge of the K-1 pulse, the counter code 3 becomes equal to the code coming from the output of the setpoint 4 of the pack start code. The first code comparison element 6 responds to the instant of equality of codes by the appearance of a signal at its output (Fig. 2.6). This triggers trigger 2 (Fig. 2, d) and opens element I 1 (fit 2, d. The impulses of the input sequence, starting with K-th, arrive at the output of element I 1 and further along bus 9 are transmitted to the consumer. The trailing edge of the gp th pulse is set to a code equal to the code on the counter 3. It arrives from the setpoint end 5 of the packet (FIG. 2, c). The second code comparison element 7 responds to the moment of equality by the appearance of a signal at its output and the trigger 4 returns return to the initial state. Element AND 1 closes and the input sequence pulses cease stumbles on its output. Thus, at the output of AND gate 1 receives pulses from the K-th to m-th inclusive.

In the presented circuit, for example, for an eight-bit counter, the implementation of the comparison circuits requires no more than six series microcircuit cases. 133 or 155 without increased integration, i.e. in comparison with the known scheme, the gain is achieved at least three times, which greatly simplifies the device and increases its reliability.

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Claims (1)

(5 7) TEMPORARY SELECTOR, containing the AND element, the output of which is connected to the output bus of the device, the first input is with the input bus of the device and the input of the pulse counter, the second input is with the trigger output, and so on and so forth that, in order to increase the reliability of the device’s operation, a packet end code generator, a packet start code generator, first and second code comparison elements, the outputs of which are connected respectively to the first and second inputs of the trigger, the first inputs are connected to the pulse output of the pulse counter second entrance first e the code comparison element is connected to the output of the packet start code generator, the second input of the second code comparison element is connected to the output of the packet end code generator.