GB1305683A - Internal delay stabilization device for transponder - Google Patents

Abstract

1305683 Radar responder INTERNATIONAL STANDARD ELECTRIC CORP 19 April 1971 [17 April 1970] 27264/71 Heading H4L A transponder adapted to respond to incoming interrogation pulse pair signals spaced according to one or more modes and to transmit after a predetermined internal delay a corresponding response code comprises: a decoder I, Fig. 3 receiving the pulse pairs at a terminal 1, and generating a specific unique recognition signal for pulse pairs conforming to one or other of the modes; a response coder II comprising a coding memory 26a, 26b storing the digits of the coded response associated with each said mode, a coding device 27a, 27b, 28, 6 for receiving the coded response digits according to the recognized mode in response to a transfer pulse specific to said mode, and a coding clock 20 of period #c started by a response triggering pulse and which controls readout of the videofrequency response pulses at the output of said coding device; the internal delay being determined by a quantized delay device, Fig. 4, connected to terminal 1 via a gate circuit and controlled by a primary clock of period #a substantially less than #c to provide a quantized delay T1 between the device's input and output terminals, being an integral multiple of #a, the gate being switched by said recognition signal so as to restrict the passage to the second pulse only of the recognized interrogation pulse pair whereby to initiate the quantized delay and the generation of the triggering pulse at the output terminals of the delay device. The quantized delay device includes: a fast shift register 45 having k stages separated into first and second groups and stepping forward a source pulse formed at its input D and having the period #a defined by a stepping clock 46; a bistable circuit 43 applying, with very short delay, the video-frequency pulses to the input of the first state of the first group of the fast shift register 45 to form said source pulse of width shorter than or equal to #a; bistables and NOR gate (37a, 37b, 40) controlled by the interrogation recognition signal controlling operation of the first stage of the second group of the fast shift register to permit the source pulse corresponding to the second pulse pair pulse to progress through the second group stages ; bistables and NOR gates 37a, 37b, 39a, 39b, responsive to the source pulse when it appears at the output of the second group of stages and which transform it into the transfer pulse, the bistables and NOR gates 37a, 37b, 39a, 29b also forming, together with bistable 49 and a synchronous divider 50, a circuit generating the response triggering pulse at the time T1 which follows the input of the second pulse of the pulse pair into the first stage of the first group. The decoder I and the response coder II utilize the same slow shift register 6 in turn, stages thereof used for the coding being equal to the maximum number of digits in the coded response, plus one; the output of the first stage of the second group of the fast shift register 45 being connected to the reset inputs C of the stages of the slow shift register 6, except to the first stage (right hand end) input; the slow shift register stage set inputs P, except for the first stage input, being connected to the corresponding outputs of the coding memory 26a, 26b via the AND gates 27a, 27b and common NOR gates 28, for simultaneously introducing, in response to application of the transfer pulse, the coded response digits into the slow shift register; and the slow shift register first stage reset input being connected to the reset inputs of the synchronous divider 50 so as to clear the shift register operation from operating as the coding device. By such digital processing the response delay of the responder is caused to have an uncertainty of only (LŒ45)ns.