SU1005030A1 - Device for extracting the extremal from n numbers - Google Patents

Description

The invention relates to automatics and computing, and can be used in the implementation of technical means to isolate an extreme from a set of numbers. A device for comparing numbers is known, containing triggers, AND, OR, elements. control and synchronization til The disadvantage of the known device is the absence on its outputs of the codes of the extremal number and but the register register storing the extreme number. The closest to the proposed one is a device for extracting an extreme of n m-bit binary numbers, containing n registers storing m-bit binary codes of comparison numbers, TL-input elements OR, grg-input elements OR, t " n three-input elements And, m input tires for supplying control signals and output signals. Direct register bits are connected to the inputs of n-input elements OR, inverse outputs of each register are connected to the first input of the corresponding AND elements, the second and third inputs of which are bit-wise connected to the input buses of control signals and to the outputs of the n-input elements OR respectively. The outputs of the n-input elements OR are also connected to the corresponding output buses of the device, and the outputs of the elements AND of each register are connected to the inputs of the t-input elements OR, the outputs of which are connected to the corresponding output of the device t2-. The purpose of the invention is to simplify the device. The goal is achieved by the fact that in a device for extracting an extremal number of n numbers, containing n input ring registers, AND control elements AND, the OR element, the result register, with the high-end output of each -th input ring register connected to the first input f-ro control element And, where i 1/2 ,. ..n p the output of each of KOTojAax is connected to the i-mu input of the OR element, the output of which is connected to the information input of the result register, 2n elements AND, n elements OR, register, mask register, analysis node, output of each i-th are entered the control element AND is connected to the first input of the m-th element AND, each f-and the output of the mask register is connected to the first input (i + n) -ro of the element AND, the second inputs 1,2,. . . , nth elements And are connected to the first input of the device record, second inputs (.n + lj, (n + 2), ..., 2nth elements And are connected to the second input of the device record, you move every i-th and (i + p) -th jTOB element AND connected to the inputs of the i-th element OR, the output of each i-ro element OR is connected to the 1st input of the registry, the i-and output of which is connected to the second input -t-ro control element And and with the i-th input of the analysis node, the first input of the device record is connected to the control input of the result register. In addition, the analysis node contains the elements AND, OR, OR NOT, the forbidden elements a, the first input of the node is connected to the first input of the first EL element OR NOT and the first inverse inputs of the first, second, third and fourth prohibition elements, the output of which is connected to the inputs of the first OR element, the second input of the node is connected to the second input of the first element OR -NOT and with the direct input of the first prohibition element, the third input of the node is connected to the first input of the second OR element and to the second inverse inputs of the second, third and fourth prohibition elements, the fourth input of the node is connected to the second input of the second OR element and direct by the entrance. the second prohibition element, the fifth input of the node is connected to the first inputs of the second and third elements OR NOT and to the third inverse inputs of the third and fourth elements of the ban, the node 1 input connected to the second inputs of the second and third elements OR NOT and the direct input of the third element prohibition, the seventh input of the node is connected to the third input of the second element OR NOT, to the first input of the third element OR, and to the fourth inverse input of the fourth prohibition element, the eighth input of the node is connected to the fourth input of the second element OR, with the second m input of the third element OR and with the direct input of the fourth prohibition element, the outputs of the first element OR NOT and the second element OR are connected to the first and second inputs of the first element AND, respectively, the outputs of the third element OR NOT and the third element OR are connected to the first and the second inputs of the second element OR, respectively, the outputs of the first and second elements AND are connected to the inputs of the fourth element OR, FIG. 1 shows a block diagram of a device; FIG. 2 - an example of the implementation of the analysis node. The device contains n input ring registers 1.12, ..., Ip / P control elements 2, 20, ... 2, 2p of blocking elements And 3, 32, ..., 3n, register 4 masks, element OR 5 , register 6, analysis node 7, result register 8, n elements OR 9 - ,, 9 2, ..., 9 п, inputs 10 and 11 of the record, outputs 12 and 13 of the device, installed inputs 14.. Node 7 analysis contains the element OR NOT 15, the elements OR NOT 16, the elements OR 17 and 18, the elements OR 19 and 20, the element OR-NOT 21, the elements 2225 prohibition, the elements And 26 and 27, the inputs 28 of the analysis node. Figure 2 shows an example of the execution of the analysis node 7, which provides you with the separation and coding of the first unit. This scheme. Built on standard functional logic elements AND, OR, OR NOT. The device operates as follows. In the initial state in the input ring registers 1.,, 1 2 ... , 1 c are the compared codes, and the reg-mask of the mask, the register of fixing the extremum and the register of the result are zero. At the beginning of the cycle of extremum extremum, according to the installation inputs 14, the number register in the mask register 4 is written comparing with e x numbers, which can be determined by the type of task performed by the computer containing the proposed device or the result of checking the registers, i.e. if one of the input registers. 1 - defective, then using the code received in the mask register, you can exclude this register from consideration. When the input of the control signal is received at the input 11 into the register 6 from the output of the And 3 elements, the contents of the mask register are overwritten. Further, when another control signal arrives at the input 10 of the recording of a different control signal, a bitwise (starting from the highest bit) comparison of the numbers begins. If the J-OM bit (, j 1,2, ..., TP) of the input ring registers 1 contains all units or units and zeros, then the control signal at the output of the element OR 5 is equal to one, and the information of the j-ro signal the input registers are taken into register b, and if in the j-th register bit 6 in the i-th cycle there is zero, then in (J + 1) -th and in the subsequent comparison cycles in the i-th bit of the register 6 will be zero , since the i-and the output of register 6 is connected to the input of the element AND, and locks it. If in the J-OM de registers 11 ,, 12,. . . , 1, all zeros, the control signal at the output of the element OR 5 is equal to zero, information is not received in register 6 in this cycle, and the result of pre-junction (j-l) -ro comparison tact is stored in register b. Next comes the comparison (j + l) -ro bit, etc. From the output of the element OR 5 information each-contact arrives at the input of the sequential reception of information of the register 8 result. The duration of the control signal applied to the input 10 of the recording is m cycles and is determined by the width of the numbers being compared. After t cycles have passed, the control signal at input 10 of the record is removed, and the comparison ends.

After the end of the comparison, in the register 6 of the fixation of the extremum there are units in those bits that correspond to the numbers of the input registers that store the extreme number. At the outputs of the analysis node 7, the unit is allocated and encoded, connected to the output buses 13 of the register number code, where the code of the first order of the register number storing the extreme number is located. At the outputs of the result register 8, connected to the output buses 12 of the extremum code, an extremal number code is found.

Consider the operation of the device on a specific example. Predopol5: im, it is necessary to select the maximum of eight 16-bit numbers. All eight input registers are healthy, so there are 4 masks in eight masks of the register 4 masks. When a control signal is applied at the input 11 of the record, the T-shirt is rewritten into register b. Next / when the control signal is applied to the input 10 of the record, a bitwise comparison is started. Let the maximum numbers be in the second and fifth input registers. After 16 comparison cycles in the register of fixing the extremum, the units remain in the second and fifth digits, i.e. In register B, position code 01001000 is present. At the output of node 7 of the analysis of the scheme for selecting and encoding the left unit, code 010 is present, and output register 8 of the result is the code of the maximum number.

The amount of equipment needed to solve this problem in the device prototype is: 8 input registers, 128 AND elements, 24 OR elements. In the series 133 (Logic) chip packages, this is 160 cases.

In the proposed device, this task requires 8 input registers, 24 AND elements, 1 OR element, 1 mask register, 1 extremum fixation register, and 1 result register. In the 133 series, this is 48 cases.

Thus, the amount of equipment in the proposed device is about 3 times less than in the device prototype. Win 1: La in the amount of equipment becomes more significant with increasing bit size by comparing. numbers, since in the proposed device only an increase in the result register size is required.

Claims (2)

1. A device for extracting an extremal of n numbers, containing n input ring registers, n control elements AND, the OR element, a result register, with the output of the high bit of each i-th input ring register connected to the first input of the i-ro control element And, where 1 1,2, ..., p, the output of each of which is connected to the i-th input of the OR element, the output of which is connected to the information input of the result register, characterized in that, in order to simplify the device, 2n are entered into it elements AND, elements OR, register, regis p masks, analysis node, the output of each i-ro control element AND is connected to the first input of the i-ro element AND, each i-and output of the mask register is connected to the first input of n + - th element AND, the second inputs 1, 2, ..., nth elements I. are connected to the first input of the device record, the second inputs (n + 1), (n + 2),. . . , 2n-th elements AND are connected to the second input of the device record, the outputs of each i-ro and (+ n) -th elements AND are connected to the inputs of the 1st element OR, the output of each i-ro element OR is connected to the 1st register input , -th output to: one that is connected to the second input of the 1st control element AND and to the 1st input of the analysis, the first input of the device record is connected to the control input of the result register. 2. Device pop. 1, which differs from the fact that in it the analysis node contains AND, OR, OR-1 elements: prohibition elements, the first input of the node connected to the first input of the first OR-NOT element and the first inverse inputs of the first , the second, third and fourth prohibition elements, the outputs of which are connected to the inputs of the first OR element, the second input of the node is connected to the second input of the first OR element and the direct input of the first prohibition element, the third input of the node is connected to the first input of the second OR element and to the second inverse inputs of the second / retego and fourth members ban fourth input node coupled to a second input of the second OR gate and a direct input of the second element the prohibition, the fifth input of the node is connected to the first inputs of the second and third elements OR NOT and to the third inverse inputs of the third and fourth elements of the prohibition, the sixth input of the node is connected to the second inputs of the second and third elements OR NOT and the direct input of the third prohibition element, the seventh input of the node is connected to the third input of the second element OR NOT, to the first input of the third element OR to the fourth inverse of the fourth prohibition element / eighth input of the node is connected to the fourth input of the second OR element, with the second input of the third the OR element and with the direct input of the fourth element of the bolt, the outputs of the first element OR NOT and the second element OR are connected to the first and second inputs of the first element AND, respectively, the outputs of the third element OR NOT and the third element OR are connected to the first and second inputs of the second element OR, respectively, the outputs of the first and second elements And connected to the inputs of the fourth element. OR. Sources of information taken into account in the examination 1. USSR author's certificate 798811, cl. G About F 7/02, 1979.  2. USSR author's certificate 514291, cl. G 06 F 7/02, 1973 (prototype). / l one one n Lr sgpg  i sh AND WE j % “JLI nil i II III iM“ i ir iliii. . "J iL wl 9i Iff i TH TIM n w -ff. eleven 3n eleven n 13 28 13 Rig.2