SU1003304A1 - Trigger device - Google Patents

Description

(5) TRIGGER DEVICE

The invention relates to a pulse technique and can be used as a memory element in devices of increased reliability - with a high intensity of interference. A trigger device is known that contains the C of the NAND element; two elements NOT and two RC circuits | 1. A disadvantage of the known device is the complexity and low reliability due to the presence of RC circuits. The closest in technical essence to the present invention is a trigger device containing two triggers, three AND-NOT elements, two AND elements and an OR 2 element. A disadvantage of the known device is the relatively low noise immunity due to the lack of control over the input durations signals triggers a device from an interfering signal according to one of the treatments when there is no signal of the second signal. The purpose of the invention is to increase the noise immunity of the trigger device. The goal is achieved by introducing a third trigger into the trigger device containing two triggers, the direct and inverse outputs of which are connected to the installation inputs 1 of the first and second trigger, respectively, the direct output of the first trigger connected to the single input (U) of the third trigger , the zero input (K) of which is connected to the forward output of the second trigger, the installation input in O of the first trigger is connected to the first input bus of the device and the information input (TE) of the second trigger, the installation input in O of which is connected to the formation input (D) of the first trigger and the second input bus of the device, and the synchronization inputs of the first, second, and third nets of the trigger are connected to the SNCh-ronization bus. In the drawing, a diagram of a three-man device is shown. The device contains triggers 1-3, buses 4 and 5 of control signals, sync bus 6, output buses 7 and 8. In the initial state, on input buses 4 and 5, single signals prohibiting switching of triggers 1 and 2 on clock pulses from bus 6 sync. The triggers 1 and 3 are in the zero state, while the three ger 2 are in an indeterminate state, i.e. At its outputs there are two single signals: at the direct output - due to a single signal at the installation input to 1 s inverse output of the trigger 3 at the immersive output - due to a single signal at the installation input to O from the input bus 5. On the front edges of the clock. the output pulses in trigger 3 will confirm the zero state, and as its single input there is a zero signal from the direct output of the trigger 1, and a zero signal on the zero input from the direct output of the trigger 2. After the zero control signal is applied to the bus 5, the inhibit signal is removed work three 2 on the installation input to O, but it is blocked by a single signal on the installation input to 1. Trigger 2 is in the single state. The clock pulses of the state of the triggers do not change. When the zero control signal on bus 5 is removed, the device returns to its original state. After a zero control signal is applied to the bus k, the trigger 1 is disabled. Since the information input of trigger 1 has a single signal (no control signal on the input bus 5), trigger switch 1 occurs on the leading edge of the first arriving clock pulse. in a single state. On the leading edge of the second clock pulse, trigger 3 is switched to a single state (in the counting mode, since there are single signals on its single and zero inputs). In this case, a single signal from the direct output of trigger 3 blocks the operation of trigger 1 on the installation input into 1, sets it to one state, and nupgvoy signal siiv (p (, my output of trigger 3 removes the blocking from trigger 2 on the mouth input - new ones in 1. Trigger 2 goes from uncertainty to zero state. The subsequent clock pulses confirm the single state of trigger 3, since there is a single signal at its single input and a zero signal at its zero input. After the termination on bus 4, the control a single signal L on the input of the installation into O puts the trigger 1 into an indefinite state. The state of the trigger 3 according to clock pulses is confirmed. After a 5-zero control signal is applied to the bus, the prohibition of the operation of trigger 2 is removed, since the information signal of the trigger 2 has a single signal (no the control signal on the input bus k), then on the leading edge of the first arrival of the clock pulse, trigger 2 is switched to the one state. On the leading edge of the second clock pulse, the trigger 3 switches to the zero state (in the counting mode, since on its single and zero inputs there are single signals). In this case, a single signal from the inverted output of trigger 3 blocks the input of the set to H trigger 2, sets it to one, and the zero signal from the direct output trigger 3 removes the lock from trigger 1 to the installation of 1. The trigger 1 passes from uncertainty state to zero state. Subsequent clock pulses confirm the zero state of trigger 3, since at its single input there is a zero signal, and at the zero input there is a single signal. Upon termination of the control signal bus 5, a single signal at the installation input at, 0 sets trigger 2 to an undefined state. The state of trigger 3 in clock pulses is confirmed. Switching r to igger 3 can start no earlier than the leading edge of the second clock pulse, after the zero control signal arrives on bus 4 (5) in the absence of a zero control signal on Bus 5 (4), therefore, the interference signals.

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having a duration shorter than the period of the clock pulses cannot switch the trigger device, since the trigger 1 (2) after the end of the interference signal is set to the initial state.

If the control inputs of the trigger device, which is in the zero (single) state, were simultaneously sent from the control or interference signal, then the trigger 1 (2) will not change its state by pulse to the pulse, since the zero state of the trigger 1 ( 2) it will be confirmed by the zero signal at its information input, and the trigger 2 (1) will then be in a single state due to a single signal at the installation input 1.

Using an additional trigger, connecting trigger synchronization inputs to a synchronization bus, and introducing new connections ensure reliable operation of the trigger device when there is interference on one of the inputs and the absence of a control signal on the other due to a delay in the input control signals and then storing the state of the additional trigger ( the first trigger performs a delay on the first control input and remembers the single state of the additional trigger, and the second trigger on the second control th entry and remembers null state additional trigger.

The use of the proposed technical solution in pulse devices

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This technology will allow to increase the reliability and accuracy of operation due to the suppression of noise on control inputs with a duration shorter than the period of the reference frequency following.

Claims (2)

1. Authors certificate of the USSR No. 600698, 1977. 2. USSR author's certificate ff 7 +3172, cl. H 03 K 3/286, 1978 (prototype). 7th S -about