SI7711979A8

SI7711979A8 - Analogous frequency converter

Info

Publication number: SI7711979A8
Application number: SI7711979A
Authority: SI
Inventors: Jan Petr
Original assignee: Landis & Gyr Ag
Priority date: 1976-08-25
Filing date: 1977-08-16
Publication date: 1994-12-31

Description

Nastavak na strani 8Continued on page 8

Pronalazak se odnesi na analogni pretvarač učestanosti.The invention is referred to an analog frequency converter.

Poznati su analogni pretvarači učestar.osti u raznevrsnim naoinima izvodjenja. Pri velikim zahtevima za tečnost, npr. za primene u statičkim električnim trojilima, danas u odnosu na druge postupke ima preimučstvo postupak kompenzacije količine punjenja i postupak izmene električnog naboja.Analog frequency converters in various embodiments are known. At high fluid requirements, e.g. for applications in static electric brackets, today, over other processes, the charge-compensation procedure and the electrical charge-change procedure are preferred.

Kod postupka kompenzacije količine naboja (npr. poznatog iz saopštenja 19 (19”2) 1 S.l? Landis & Gyr, integriše se merna struja u integratoru i pri dostizanju odredjenog napona, integratoru se oduzima konstantni kompenzacioni naboj. Izmedju dovedenog i oavedenog naboja uspostavlja se ravnoteža, pri. čemu je broj naboja kompenzacije u jedinici vremena proporcionalen merr.oj struji. Sadržaj punjenja pojedinačnih kompenzacionih impulsa predstavlja mernu konstantu i može jednostavnim sredstvima da se održava konstantnem sa velikem tačnošcu. Suprotno torne, potrebne su naročite mere da bi se sprečio prazan hod analegnog pretvarača učestanosti. Kod postupka izmene električnog naboja (npr. poznatog iz DT-OS 1 946 245) , merna struja se takodje integriše u integratoru; pri dostizanju gornje vrednosti praga napona integratora, menja se polaritet merne struje i na taj način se preokreče smer integracije. Broj izmena naboja u jedinici vremena proporcionalen je merrioj struji, Kapacitet kondenzatora, kao i razlika izmedju gornje i donje vrednosti praga, predstavljaju kod postupka električnog naboja merne konstante, koje vrlo teško mogu da se održavaju konstantnim sa potrebnom digitalnom stabilnošču. Suprotno torne, automatski se sprečava prazni hod analogneg pretvarsča učestanosti. Kod primene ovakvog analegnog pretvarača učestanosti u statičkom električnom brejilu, periodičnim prekopčavanjem polariteta mogu delimično da se kompenzuju struje kvara koje ne zavise od preključivanja polariteta i da se na taj način proširi područje merenja. Osnovni zadatak pronalaska je da spoji preimucstva postupka kompenzacije punjenja i postupka izmene električnog naboja i da na taj način stvori analogni pretvarač učestanosti čija je merna konstanta data sadržajem punjenja kompenzacionih impulsa i koji može da se kompenzuje pri strujama greške kao i da se automatski spreči prazan hod.In the charge compensation procedure (eg known from press release 19 (19 ”2) 1 Sl? Landis & Gyr, the measuring current is integrated in the integrator and when a certain voltage is reached, the integrator is deprived of a constant compensating charge. equilibrium, whereby the number of charge charges in a unit of time is proportional to the measuring current The content of charge of the individual compensation pulses is a measuring constant and can be kept constant with great accuracy by simple means. In the process of changing electrical charge (eg known from DT-OS 1 946 245), the measuring current is also integrated in the integrator; when reaching the upper value of the integrator voltage threshold, the polarity of the measuring current is changed and thus reversed the number of charge changes in a unit of time is proportional to the merry current, The capacitance of the capacitors, as well as the difference between the upper and lower threshold values, are, in the process of electric charge, a measuring constant, which can hardly be kept constant with the required digital stability. On the contrary, the analogue frequency converter is automatically prevented from idling. With the use of such an analogue frequency converter in a static electric buzzer, periodic switching of polarity can partially compensate for fault currents that do not depend on polarity switching and thus extend the measurement range. The basic object of the invention is to combine the advantages of the charge compensation procedure and the electric charge modification process, thereby creating an analog frequency converter whose measurement constant is given by the charge content of the compensating pulses and which can be compensated for by fault currents and automatically prevent idle time .

Pronalazak se sestoji u odlikama naznačenim u karakteriSučem delu patentnog zahteva 1.The invention consists in the features indicated in the characterization of claim 1.

U nastavku če se na osnovu erteža objasniti primeri načina izvodjenja pronalaska. Slike prikazuju;In the following, examples of how the invention will be performed will be explained on the basis of the drawing. Pictures show;

Sl. 1 šemu veza statičkog meraoa snage sa analognim pretvaračem učestanosti,FIG. 1 diagram of the connection of a static power meter to an analog frequency converter,

Sl. 2 dijagram impulsa analognog pretvarača učestanosti prema sl.FIG. 2 is an impulse diagram of an analog frequency converter according to FIG.

1,1,

Sl. ? varijantu spoja za upravljanje, Sl. 4 dijagram impulsa analegnog pretvarača učestanosti prema sl. 1, sa spojem za upravljanje prema sl. ? iFIG. ? a control joint variant, FIG. 4 is a diagram of the impulse of the analogue frequency converter according to FIG. 1, with the control connection of FIG. ? i

Sl. 5 šemu veza dodatnog uredjaja.FIG. 5 Connection diagram of the optional device.

Na sl. 1 eznačava 1 multiplikator koji na ulaz analogneg pretvarača 2 učestanosti daje mernu struju 1^. Merna struja I proporcionalna je proizvodu napona’ U i. struje I. Multiplikator 1 ima upravljački ulaz ? na koji se dovodi signal P polariteta. Sa cvim signalom polariteta može da se priključi predznak množenja, a na taj način polaritet merne struje 1^. Prekijučivanje polariteta može da se izvrši na poznati način npr. menjanjem polariteta napona U iii struje I, iii digitalnom inverzijom signala u multiplikatoru 1.In FIG. 1 denotes 1 multiplier which gives a measuring current of 1 ^ to the input of an analog converter 2 of frequency. Measurement current I is proportional to the product of voltage 'U i. current I. Multiplier 1 has a control input? to which the P polarity signal is fed. With the polarity signal, the multiplication sign can be connected, thus the polarity of the measuring current is 1 ^. The polarity reversal can be done in a known manner e.g. by changing the voltage polarity U iii of current I, or by digital inversion of the signal in multiplier 1.

Analogni pretvarač 2 učestanosti sastoji se u sustini od integratora 4, spoji) 5 za upravljanje i davača 6 kompenzacionog punjenja. U prikazanom primeru integrator 4 je obrazcvan od pojačavaoa 7 i kondenzatora 8 uključencg u njegovo kolo povratne sprege.The analogue frequency converter 2 consists essentially of an integrator 4, a control unit 5 and a compensating charge encoder 6. In the example shown, the integrator 4 is formed by an amplifier 7 and a capacitor 8 included in its feedback circuit.

Izlaz integratora 4 priključen je na prekidač 9 prage, koji ε jedne strane služi na poznati načir, za isključivanje impulsa kompenzacije punjenja, a s druge je sestavni deo spoja 5 za upravljanje koji stvara signal P polariteta. U primeru na sl.The output of integrator 4 is connected to a threshold switch 9, which ε serves on one side in a known manner, to exclude charge compensation pulses, and on the other is an integral part of control circuit 5 that generates a P polarity signal. In the example in FIG.

piekiclač 9 praga je koroparator napcna sa jedr.cir. jedinom vrednošču ϋθ praga.piekiclač 9 threshold is a coroparator filled with a sail. the only value of the ϋθ threshold.

Spoj 5 zs upravljanja ima dalje relaksacioni stepen 10 sa dva ulaza 11, 12 i jedrim izlazom 1.?. Za ovaj relaksacioni stepen, koji može da bude sastavljen cd PS-okidača i dvaThe 5 zs control compound has a further relaxation stage 10 with two inputs 11, 12 and a single output 1.?. For this relaxation stage, which can be composed of a cd PS trigger and two

uzajamno spregnuta ulazna gejta važi tabela a mutually coupled input gate is a valid table K K Z Z P P 0 0 0 0 X X 0 0 3 3 3 3 0 0 3 3 3 3 3 3 C C C C 3 3 1 1 X X pri čemu whereby K znači K means signal na ulazu 31, Z signal at input 31, Z signal signal na on ulazu 32, P signal input 32, P signal polariteta na polarity at izlazu 1? i X predjašnje exit 1? and X previous stanje. state. Ulaz Entrance 33 33 rejsksacionog stepena of reyxation degree spojen connected je sa is with izlazom prekidača 9 switch output 9 praga, a threshold, a ulaz entrance 3 2 3 2 sa. izlazom stepena 14 with. exit grade 14

reduktora. Odnos h delite]ja stepena 34 reduktora paran je brci i jednak je iii veči cd dva.gearbox. The ratio h of dividing the gear 34 of the gear unit is even and is equal to or greater than cd two.

Dva I-gejta 35, 36 obrazuju od signala K, Z i P dva signala L i M. Pored toga, oba ulaza 3 3 , 3 2 i izlaz 1? relaksacicncg stepena p priključena su na tri ulaza I-gejta 15 kao i na tri invertujuča ulaza 1-gejta 16. I-gejt spojen je na isključncm ulazu 17 za pozitivne impulse punjenja, a I-gejt na isključri ulaz 18 za negativne impulse punjenja kompenzacionog davača 6 punjenja.The two I-gates 35, 36 form two signals L and M. from the K, Z, and P signals. In addition, both inputs 3 3, 3 2 and output 1? the relaxation degrees p are connected to the three inputs of the I-gate 15 as well as to the three inverting inputs of the 1-gate 16. The I-gate is connected at the off-port 17 for positive charge pulses, and the I-gate at the off-input 18 for negative charge pulses of the compensation encoder 6 charge.

Isključni ulazi 37, 38 davača 6 kompenzacionog punjenja vode po jednom D-ulazu D-okidača 39, i 20, čiji taktni ulazi su spojeni sa kvarcr.im štabi lizujuč im oscilatorom 21 vremenske baze. Na izlazu₊okidača 19 odn. 20 nastaje signal I cdn. I , koji preko prekidača 22 cdn. 2? spaja izvor 24 konstantne struje 24. Izvor 24 konstantne struje £aje pozitivnu referent.nu st ruju I , a izvor 25 konstantne struje negativnu referentnu struju I na ulaz integratora 4. Izlazi okid.ača 19, 20 dalje su spojeni sa ILI-gejtom 26. ILI-gejt 27 je na ulaznci strani spojen sa izlazima 23 oscilatora vremenske baze i ILI-gejta 26. ILI -gejt Σ'¹ daje izlazni Signal F ne izlaz 28 analognog pretvarača 2 učestanosti.The exclusive inputs 37, 38 of the encoder 6 of the compensating water charge per D-input of the D-trigger 39, and 20, the clock inputs of which are coupled to the quartz headquarters by lysing the time-base oscillator 21. At exit ₊ trigger 19 or. 20 produces a signal I cdn. And, which via switch 22 cdn. 2? connects DC 24 source 24. DC 24 source positive reference reference I, and DC constant 25 negative reference current I to integrator 4. The outputs of trigger 19, 20 are further connected to the OR gate 26 The IL-gate 27 is connected at the entry side to the outputs of the time-base oscillator 23 and the IL-gate 26. OR-gate ¹ ' ¹ gives the output Signal F not the output 28 of the frequency converter 2.

Kao što je naznačeno na sl. 3, izlaz 28 koji vodi. signal F, može da bude spojen sa stepenoir. 14 reduktora, Dalje stepen 3 4 reduktora može da se upravlja referentnim signalom P osoilatora 23 vremenske baze, iii nekom drugom konstantnom učestanošču. Konačno. stepen 14 reduktora može da se izostavi i da se signal Z napaja na upravljački spoj 5 pogodno izabranom konstantnom učestanošč u spolj a.As indicated in FIG. 3, output 28 leading. signal F, can be coupled to a stepper. 14 gearboxes, Further stage 3 4 gearboxes can be controlled by the reference signal of the P oscillator 23 of the time base, or some other constant frequency. Finally. the gear unit stage 14 can be omitted and the signal Z is fed to the control circuit 5 with a suitably selected constant frequency at the outside a.

U nastavku če se na osnovu sl. 2 objasniti način rada opisanog analognog pretvarača učestanosti za slučaj da se signal F napaja u stepen 34 reduktora, a da je N=4. Sl. 2 pokazuje vremensko trajanje izlaznog n.apona U^ integratora 4 kao ₊i digitalne signale R, K, Z, L, M, I , I i F pri konstantnoj merno j strujiBelow, based on FIG. 2 explain the operation of the described analog frequency converter in case the signal F is fed to the gear unit stage 34 and N = 4. FIG. 2 shows the time duration of the output n.voltage of U ^ integrator 4 as ₊ and the digital signals R, K, Z, L, M, I, I and F at a constant measuring j current

VV

Ciklus prekopčavenja je dat penodom signala P polariteta, koji počinje u trenutku t i završava se u trenutku t,„. U prvom poluperiodu t do t_ merna struja I je negativna, a u drugom poluperiodu t^ dc t je pozitivna. Fosle premene polariteta, koju u trenutku t prouzrokuje signalThe switching cycle is given by the pole P signal, which starts at time t and ends at time t, ". In the first half-period t to t_ the measuring current I is negative and in the second half-period t ^ dc t is positive. The pole of a polarity change caused by a signal at time t

P polariteta, ras^e izlazni napen U usled negativne merne struja I prvo kratkotrajno, tako da signali K i L imaju logičnu vrednost 1, dok u trenutku t sledeči bok porasta referentnog signala R ne izvrne okidačP polarity increases the output voltage U due to the negative measuring current I first briefly, so that the signals K and L have a logical value of 1, until at the moment t the next side of the rise of the reference signal R turns the trigger

39, prekidač 22 se zatvori i uključen je pozitivni izvor 24 konstantne struje. Od ovog trenutka t , opada izlazni napon U usled toga št<£ pozitivna referentna struja I dominira u odnosu na mernu struju I:39, switch 22 is closed and a positive DC source 24 is switched on. From this moment t, the output voltage U decreases, as a result, st <£ the positive reference current I dominates with respect to the measuring current I:

M pri opadanju ispod vrednosti o praga, prelaze signali K i L na logično O, što se najpre ne ispoljava. u trenutku t„ izvrce se okidač 39 drugim rastučim bokom referentnog signala F u položaj mirovanja i usled tega se izvor 24 konstantne struje ponovo iskopčava. Uključivar.je i isk3 jučivanje izvora 24 (signal I ) konstantne struje ponavlja se još jednem u trenutku t_? i t^.M, when falling below the threshold o value, exceeds the K and L signals to logical O, which is not manifested first. at time t 'the trigger 39 is turned off by the second side of the reference signal F to the idle position and the constant current source 24 is switched off again. Is the source 24 (constant current signal I) of the DC 24 repeated at another time t _? it ^.

Ze vreme do sada opisanog toka rada uvek su u toku vremena preklapar.ja impulsa signala Ril davana dva izlazna impulsa (signal F) na izlazu 28, kao i na stepenu 34 reduktora. Pri nestajanju drugog izlaznog impulsa, prelazi signal Z na izlazu stepena 14 reduktcra na logično 0. Ovo prouzrokuje da kod sledečeg prekoračenja napona U praga u trenutku t prekidač fo izvrtanja odmah izvrže, signal P polariteta prelazi na logično 0, a merna struja I usled toga menja pclaritet, tj. postaje pozitivna. Za vreme drugog poluperioca signala P polariteta, ponavlja se opisani tok ss pozitivnem mernom strujom 1_M i negativnom mernom strujom I . Na dijagramu na sl. 2 lake se viai da signal polarizacije P, koji upravlja pelaritetom merne ^truje 1^, kao i referentne struje I_r odn. I davača 6 kompenzacionog punjenja uvek menja svoju logičnu vrednost pri jednakom nivcu U izlaznog napona i na taj način tačno pedešava bilans punjenja koje dotiče sa mernom strujom 1^ i otiče sa referentnom strujom I posle svakog poluperieda signala F polarizacije. Na taj način se osigurava da usled periedičnog preključivanja polariteta ne može da nastane nikakva greška merenja usled gubi taka punjenja.Over the course of the workflow described so far, two output pulses (signal F) at output 28, as well as at the gear unit 34, have always been switched over time. When the second output pulse disappears, the signal Z at the output of stage 14 of the reducer goes to logical 0. This causes the next time limit of the threshold U to be turned off immediately at time t, the polarity switch P switches to logical 0, and the measuring current I consequently. changes the pclarity, i.e. becomes positive. During the second radius of the P polarity signal, the described current is repeated with a positive measuring current of 1 _M and a negative measuring current of I. In the diagram in FIG. 2, it is easy to say that the polarization signal P, which controls the pelarity of the measure- ment 1 ^, as well as the reference currents I _r or. The compensating charge encoder 6 always changes its logic value at the same level U of the output voltage, thus accurately mixing the charge balance that touches the measured current 1 ^ and goes with the reference current I after each half-period of the polarization signal F. This ensures that periodic switching of the polarity does not result in any measurement error due to the loss of such charge.

Preključivanje polariteta prouzrokuje automatsko prigusivanje praznog hoda. Kada naime merna struja I opadne ispod vrednosti struje ‘ greške, nezavisne cd polariteta, koja teče prema integratoru, integrator 4 se najkasnije posle sledečeg priključivarje polariteta dovodi u zasičeno stanje.The polarity switch causes the idle to automatically damp. When the measuring current I falls below the value of the fault current 'independent cd polarity flowing towards the integrator, integrator 4 is brought to a saturated state at the latest after the next polarity connector.

Periodičnim priključivanjem polariteta kempenzuje se u največoj meri usticaj struje greske, koja se superponira mernej struji I . na izlaznu * M učestanost analegneg pretvareča 2 učestanesti. Nedjutim pri preključivanju polariteta upravljanom izlaznom učestanošču, svakakc ne nastaje potpuna kompenzacija, jer poluperiodi signala P polariteta postaju nejednaki usled struje greške.Periodically connecting the polarity compensates for the maximum effect of the fault current, which is superposed to the lower current I. to output * M frequency of analogue converter 2 frequency. However, when switching the polarity with a controlled output frequency, no full compensation is certainly created, since the half-periods of the P polarity signal become unequal due to the fault current.

Pri tora relativna oreška F , iznosi rel rel pri čemu 1^ označava struju greške. Potpuna kompenzacija uticaja struje greške, nezavisne od polariteta, na izlaznu učestanost može da se postigne, ako je preključivanje polariteta doduše izvedeno od konstantne učestanosti, ali se sinhronizuje sa izlaznom učestanošču analognog pretvarača učestanosti. Pri torne učestanost prekljivanja polariteta mora da bude manja od najmanje izlazne učestanosti koja nastaje. Usled sinhronizovanja podležu poluperiodi preključenja polariteta statičkom rasipanju jednakom trajanju perioda izlazne učestanosti. Posle dovoljno dugog perioda biče medjut im srednja vrednost dva poluperioda preključivanja polariteta jednaka i na taj način če se utj caj struje greške potpuno kompenzovati.For tora the relative nut F, is rel rel where 1 ^ denotes the fault current. Complete compensation for the influence of a polarity-independent error current on the output frequency can be achieved if the polarity switch is derived from a constant frequency, but is synchronized with the output frequency of the analog frequency converter. In the case of polarity, the frequency of polarity overlap must be less than the minimum output frequency that occurs. Due to synchronization, the polarity switching periods are subject to static scattering equal to the duration of the output frequency period. After a sufficiently long period, however, the mean of the two polarity switching halves will be equal, and thus the effect of the fault current will be fully compensated.

Ovakav rad če se postiči ako se konstanta učestanosti referentnog oscilatora uvodi u stepen 14 reduktora. Pripadajuči dijagram impulsa ove alternative razlikuje se cd dijagrama impulsa na sl. 2 samo po torne, što je signal Z u potpunosti nezavisan od signala F, a broj izlaznih impulsa po poluperiodu signala P polarizacije ne mora da bude jednake veličine.Such work will be achieved if the frequency constant of the reference oscillator is introduced into the gear unit 14. The corresponding impulse diagram of this alternative differs from the cd impulse diagram in fig. 2 only, which is the signal Z completely independent of signal F, and the number of output pulses per half-period of the polarization signal P does not have to be the same size.

Umesto signala F, kao izlazni signal analognog pretvarača učestanosti može da se primeni i signal P polarizacije. Suprotno učestanosti signala F, učestanost signala P polarizacije ne podleže kratkotrajnim kolebanjima usled sinhronizovanja sa referentnim signalom R, ali uprkos torne ima čvrsti odnos prema rasiproj učestanosti signala F.Instead of signal F, the polarization signal P may be used as the output signal of the analog frequency converter. Contrary to the frequency of the signal F, the frequency of the polarization signal P is not subject to short-term oscillations due to synchronization with the reference signal R, but despite the friction, it has a firm relation to the frequency distribution of the signal F.

Na sl. 3 prikazan je upravljački spoj 5', koji može da se primeni umesto upravljačkcg spoja 5 u uredjaju prema sl. 1. Kao prekidač 9' prega predvidjen je Šmitov okidač sa goinjom i donjom vrednošču praga. Kolo 5' za upravljanje sadrži dalje stepen 29 reduktora, čiji je odnos delioca označen sa N', D-okidač 30 i dva i-gejta 31 i 32. Izlaz prekidača 9' spojen je sa ulazom stepena 29 reduktora i sa taktnim ulazom D-okidača 30, čiji je D-ulaz priključen i na izlaz stepena 29 reduktora. Signal na izlazu prekidača 9' praga označen je opet sa S. Na izlazu stepena 29 reduktora nastaje signal A, a na izlazu D-okidača 30 signal polarizacije P, stepen 29 reduktora reaguje na opadajuče tokove signala S, a D-okidač 30 na rastuče tokove signala S.In FIG. 3 shows the control connection 5 ', which can be applied instead of the control connection 5 in the apparatus according to FIG. 1. As a 9 'switch, a Schmidt trigger with a slide and a lower threshold value is provided. The control circuit 5 'further comprises a gear unit stage 29, whose divider ratio is denoted by N', a D-trigger 30 and two i-gates 31 and 32. The output of the switch 9 'is connected to the input of the gear unit stage 29 and to the clock input D- trigger 30, whose D-port is also connected to the output stage 29 of the gear unit. The signal at the output of the switch 9 'of the threshold is again marked by S. At the output of stage 29 of the gear unit signal A is generated, and at the output of the D-trigger 30 the polarization signal P, the stage 29 of the gear unit responds to the decreasing currents of the signal S, and the D-trigger 30 to the rising signal currents S.

Izlaz prekidača 9' praga spojen je i sa ulazom I-gejta 31 i invertujučim uležem I-gejta 32. Dalje je izlaz stepena 29 reduktora priključen na još jedan ulaz I-gejta 3], a izlaz D-ckidača ?C na jot jedan invertujuči ulaz. I-gejta 32. Na izlazima oba I-gejta 31, 32, koji se spajaju sa isključniir. ulazima 1”, 18 daveča 6 kompenzacionog punjenja (sl. 1.) nastaju signali L i M.The output of the switch 9 'of the threshold is also connected to the input of the I-gate 31 and the invert bearing of the I-gate 32. Further, the output of stage 29 of the gear unit is connected to another input of the I-gate 3], and the output of the D-switch? C to another invert entrance. I-Gates 32. At the exits of both I-Gates 31, 32, which are connected to the excl. inputs 1 ”, 18 of the compensator 6 sensor (Fig. 1) produce L and M signals.

Na sl. 4 prikazan je pripadajuči dijagram impulsa za slučaj N'=4. Histerezis, tj. razlika izmedju gornje vrednosti L¹ praga i dcnje vrednosti U praga prekidača 9' praga označena je sa delta u. Preključivanje polariteta nastaje uvek tačno tada, kada izlazni napon integratora 7 dostigne gornju vrednost U praga. Pri dostizanju vrednosti praga U idn. U , uključuje se dalje izvor 2 2 odn. $5 konstantne struje i time se održava izlazni napon integratora 4 unutar histerezisa delta u. UkljuČivanje i isključivanje izvora 24, 25 konstantne struje sinhronizovano je sa referentnim signalom R o zato je na sredini usporen za trajanje poluperioda referentnog signala, usled čega učestanost referentnog signala tr^ba da bude dovoljno velika u odnosu na učestanost signala P polariteta. U dijagramu impulsa naznačeni su referentni signal R i izlazni signal F poljima sa uporednim črticama, da bi se na taj način izrazila velika učestanost referentnog signala.In FIG. Figure 4 shows the corresponding impulse diagram for the case N '= 4. Hysteresis, ie. the difference between the upper value L ^{1 of the} threshold and the lower value U of the switch 9 'of the threshold is indicated by delta u. The polarity switch always occurs exactly when the output voltage of the integrator 7 reaches the upper value of the U threshold. When reaching the threshold value U and so on. In, the source 2 2 or the source is included. $ 5 constant current and thus maintains the integrator output voltage 4 inside the delta hysteresis. Turning the constant current source 24, 25 on and off is synchronized with the reference signal R o, so it is mid-delayed for the duration of the reference signal half-life, which causes the frequency of the reference signal to be sufficiently high relative to the frequency of the P polarity signal. The impulse diagram indicates the reference signal R and the output signal F in fields with parallel lines, in order to express the high frequency of the reference signal.

U po jedir.cstima se debija sledeči vremenski tok za vreme jednog perioda signala F polariteta: Od trenutka t , kada je polaritet bas preključen i sa zanemarljivim kašnj^njem je isključen negativni izvor 25 konstantne struje i uključen pozitivni izvor 24 konstantne struje, puni se integrator 4 referenstnom strujom I koja sada preovladjuje. Izlazni napor. U epada, dok u trenutku t prekidač 9' 'praga ne dostigne donju vrednost U praga i ponovo se ne isključi izvor 24 konstantne struje. U intervalu vremena t_Q do t predaje se na integratoru 4 paket ^J konstantnih kompenzacionih punjenja bez praznina i jednak broj izlaznih impulsa (signal F) na izlazu 28 analognog pretvareča 2 učestanosti. Od trenutka t ponovo raste izlazni napon U , jer sada teče samo negativna merna struja I prema integratoru 4. U trenutku ponovo se uključuje pozitivni izvor 24 konstante struje, a u trenutku se ponovo isključuje. Stepen 29 reduktora izvrče u trenutku t^, usled čega je D-okidač 30 pripremljen za izvrtanje. Cimizlazni napen U dostigne u trenutku t gornju vrednost U praga prekidača 9 , cdir.ah se izvrče Č-okidač 30, menja se signal P polariteta i menja se polaritetThe following time course is debuted in the sails during one period of the F polarity signal: From the moment t, when the polarity of the bass is switched off and with negligible delay, a negative constant current source 25 is switched off and a positive constant current source 24 is turned on. integrator 4 by the reference current I now prevailing. Exit effort. In the event that, at time t, the switch 9 '' of the threshold reaches the lower value of the U threshold and the DC source 24 is switched off again. In the time interval t _Q to t, a packet ^{J of} constant compensation charges with no gaps and an equal number of output pulses (signal F) at the output 28 of the analog converter 2 of frequency are transmitted on integrator 4. From the moment t the output voltage U rises again, because now only the negative measuring current I flows towards integrator 4. At the moment, the positive source 24 of the constant current is switched on again, and at the moment it is switched off again. The gear unit stage 29 turns out at time t ^, which causes the D-trigger 30 to be prepared for drilling. The cyclical voltage U reaches at time t the upper value U of the threshold of switch 9, cdir.ah the Č-trigger 30 is turned off, the polarity signal P is changed and the polarity is changed

M' merne struje I . Kernom strujom I koja je sada pozitivna, upravlja se integrator 4 prema denjoj vrednosti 0 praga prekidača 9'M 'measuring currents I. The core current I, which is now positive, is controlled by the integrator 4 according to the given value 0 of the switch threshold 9 '

U vremenskim intervalima t.At time intervals t.

do % ' uključen je negativni t_n do izvor čegato% 'a negative t _{n is included} to the source of what

2?2?

se konstantne struje, izlazni napon usledis constant current, output voltage due to

U P^ren!a 9°^rnj°j vrednosti υθ praga. U tački t ponovo se menja signal P polariteta, tako da počinje novi period.UP ^{ren! A} 9 ° ^rn j ° j values of υθ threshold. At point t, the polarity signal P changes again, so that a new period begins.

Odnos redukovanja N' stepena 29 reduktora mora takodje da bude paran broj i da bude jedna iii veči od dva. Izborom ovog odnosa redukovanja utvrdjuje se broj paketa kompenzacionih punjenja po periodu prekopčavanja signala P polariteta. Ne postoji tečna zavisnost učestanosti signala P polariteta i izlazneg signala F.The reduction ratio N 'of degree 29 of the gear unit must also be an even number and be one or more than two. Selecting this reduction ratio determines the number of compensation charge packets per switching period of the P polarity signal. There is no liquid dependence on the frequency of the P polarity signal and the F output signal.

Opisani analogni učestanosti prema sl. 1 sl. 1 i 3, mogu jednostavr.im dodatnim sreestvima da se modifikuju tako, da mogu da preradjuju kako pozitivne, take i negativne merne struje I (tj. u prikazanem primeru pozitivne i negativne vrednosti proizvoda U.l). Sl. 5 prikazuje primer dodatneg uredjaja pogodnog za ovo. Dva prekidača praga u obliku Šmitovcg okidača 33, 34 priključeni su ulaznim stranama na integrator 4 (sl. 1), a učestanosti pretvarači kao i prema izlaznim stranama preko ILI-gejta 35 na relaksacioni stepen 36. Vrednosti praga Šmitovog okidača 33 leže iznad, a vrednosti praga Šmitovog okidača 34 ispod vrednosti praga prekidača 9 odn. 9'. praga. Izlaz Šmitovog okidača 33 odn. 34 spojen je sa jedrim ulazom ILI-gejta 37 odn. 38, uključenim u provodnik koji vodi signal I odn. I za upravljanje prekidača 22 odn. 23. Izlaz relaksacionog stepena 36 priključen je na EKSKLUZIVM-lLI-gejt 39, uključen u upravljački ulaz 3 multiplikatore.1.The analogue frequencies described in FIG. 1 fig. 1 and 3, they can be modified by simple fortunes so that they can process both positive, negative and negative currents I (ie, in the example shown, the positive and negative values of U.l). FIG. 5 shows an example of an additional device suitable for this. Two threshold switches in the form of the Schmitt trigger 33, 34 are connected to the input sides of the integrator 4 (Fig. 1), and the frequency converters as well as the output sides via the ILI gate 35 to the relaxation step 36. The threshold values of the Schmitt trigger 33 lie above, and the threshold values of the Schmitt trigger 34 below the threshold value of the switch 9 or. 9 '. threshold. The output of the Schmitt trigger 33 or. 34 is connected to a single OR gate gate 37 or. 38, included in the conductor conducting the signal I or. And for switch operation 22 or. 23. Relaxation stage output 36 is connected to EXCLUSIVE-ILI-gate 39, included in the control input of 3 multipliers.1.

Kod premene merne struje I keja nije M prouzrckcvans signalom F polariteta, izlazni napon U raste iii epada dotle, dek ne reaguje jedan od Šmitovih okidača 3? iii 34. Na taj način se uključuje pridodati izvor 24, cdr,. 25 konstantne struje, delimično se prazni kondenzator 8 integratera 4, a izlazni napen U se vrača na visinu ncrir.alncg radnog područja. Kod vračanja odgovarajuceg Šmitovog okidača 33 odn. 34 izvrče se relaksacioni stepen 36 i signal P' polariteta na upravijačkom ulazu 3, a time se dopunski menja i polaritet merne struje I . Signal E na izlazu relaksacionog stepena 36 pokazuje smer merne struje I nezavisan od preključenja polariteta.When the measuring current I is switched, the quay is not M caused by the F polarity signal, the output voltage U rises or the epada until one of the Schmidt triggers 3 reacts? iii 34. In this way it is included to add source 24, cdr,. 25 constant, the capacitor 8 of the integrator 4 is partially discharged, and the output voltage U returns to the height of the ncrir.alncg work area. When returning the appropriate Schmidt trigger 33 or. 34, the relaxation step 36 and the polarity signal P 'at the control input 3 are inverted, thereby further changing the polarity of the measuring current I. Signal E at the output of relaxation step 36 indicates the direction of the measuring current I, independent of polarity switching.

Opisani analogni pretvarač učestanosti ima preimučstvo u odnosu na poznata rešenja, koja prema uobičajenom postupku kompenzacije punjenja rade bez preključenja polariteta, što se kompenzuju struje greške nezavisne od polariteta i. na taj r.ačin se postiže veča tačrost merenja i veča dinamika. Fored tega, autematski se sprečava prazan hod. Kod poslednje opisane varijarte, pogodne za pozitivne i negativne merne struje, postiže se savršena simetrija za oba smera struje i tada, kača I i I dve izvora 24, 25 konstantne stxu}e nisu jednake veličine, npr. zbeg pojave starenja.The described analog frequency converter has an advantage over the known solutions, which, according to the conventional charging compensation procedure, operate without polarity switching, which compensate for fault currents independent of polarity and. this results in greater measurement accuracy and greater dynamics. In addition, idling is automatically prevented. In the last variant described, suitable for positive and negative currents, perfect symmetry is achieved for both directions of current and then, snake I and I of two sources 24, 25 of constant current are not of the same size, e.g. escaping the onset of aging.

U odnosu na poznata rešenja koje rade prema postupku zamere električncg naboja, odlikuje se opisani analogni pretvarač učestanosti preimučstvom što je merne konstanta deta sadržajem naboja kompenzacionih impulsa. Ovaj sadržaj naboja može da se održava konstantnim jednostavnim sredstvima sa velikom tačnošču i dugoročnom stabilnošču. Dalje se u odnosu na postupak izmene električnog naboja dobija veča sloboda dimenzionisanja, ako se zahteva visoka izlažna učestanost. Konačno postoji pokazana mogučnest da se potpuno kompenzuje uticaj struje greške nezavisne od polariteta.In relation to known solutions operating according to the method of measuring electric charge, the described analog frequency converter is distinguished by the advantage that the measuring constant is detained by the charge content of the compensation pulses. This charge content can be kept constant by simple means with great accuracy and long-term stability. Further, greater freedom of sizing is obtained in comparison to the process of electrical charge modification if a high output frequency is required. Finally, there is a demonstrated possibility to fully compensate for the influence of the polarity-independent error current.

Prema našem današnjem znanju, za velike količine je ekonomski nejpovoljniji način primene predmeta ove pat. prijave da se ceo - u patentnej prijavi iserpno cpisani-elektronski sklop izradi kao LSI kolo. Cva integracija velike razmere, (large scale integral ion) mera da buče preuz^tii od Strane nekog iskusnog proizvodjača poluprevodnika. Dolaze u obzir svetski poznate firme, kac npr. Philips, Motorola, RCA, National Semiconductors USA. Svi opisani elementi kola megu se, medjutim, da nabave i pojedinačno, iii kac· integrisani podsklopovi u specijalizcvanim, stručnim trgovinama. Za male serije iii za opitne konstrukcije mogu se stoga lemljenjem tih elemenata na pleču štampanog kola, koja je izradjena na poznat način, da primene ekonomski najpovoljnije propisi. za koriščenje, koje preporučuje proizvodjač, i da se prema opštem inženjerskom znanju tako da prilagede jedni na druge, da se udcvolji specifikacijama proizvediače. Izbor konstruktivnih elemenata vrši stručnjak prema cilju primene analcgno-frekvencijskeg pretvarača i prema zahtevanem standardu kvaliteta, a cdredjivanje radnih pedataka vrši se za kenkretan slučaj primene, na esnevu opštih znanja u štruci.To our knowledge today, for large quantities, it is the most economically advantageous way to apply the subject of this pat. applications to have the whole - in the patent application - an elaborately scribed-electronic assembly made as an LSI circuit. A large scale integral ion is a measure to make the noise take over from an experienced semiconductor manufacturer. World-renowned companies are coming into view, such as Philips, Motorola, RCA, National Semiconductors USA. However, all of the circuit elements described above can be purchased individually or as integrated sub-assemblies in specialist, specialist stores. For small series iii for test structures, therefore, soldering of these elements on a printed circuit arm, which is made in a known manner, can be applied to the most economically advantageous regulations. for use as recommended by the manufacturer, and according to general engineering knowledge so as to adhere to each other, to meet the specifications of the manufacturer. Selection of structural elements is made by an expert according to the purpose of application of the analogue-frequency converter and according to the required quality standard, and cddating of working pedagogues is done for a specific case of application, based on the general knowledge in the field.

Claims

PATENT REQUIREMENTS

1. Analog frequency converter for trimming the output frequency proportional to the measuring current and measuring tension according to the process of compensation of the amount of charge, with integrator, threshold switch connected behind it and suppress compensating mating which gives a constant compensating charge to the capacitor of the integrator in the face of initiator switch initiation , that the analog frequency converter (2) consists of pcd circuits (6), (5) and (4), and a polarity switch (1) is connected to the input of the analog frequency converter (2), that the sub-assembly of the compensating charge encoder (6 ) contains two constant current sources, a positive constant current source (I _R ) (24) and_ a negative constant current source (I _R ) (25) that are connected to r ^ d via switches (22) and (2?), and under - the 15: 5 'control circuit assembly is connected to the threshold switch output (9: 9') such that one output of the control circuit polarity (P) (5: 5 ') is connected to the control input (?) of the polarity switch (1). and that the control circuit (5: 5 ') is connected to the exclusive inputs <= (3 7:18) of the compensation purge encoder (6).

An analog frequency converter according to Claim 3, characterized in that the threshold switch (9: 9 ') is an integral part of the control circuit (5: 5') and that one threshold switch output (9: 9 ') is connected to one entrance of relaxation stage (30:30).

An analog frequency converter according to Claim 2, characterized by m e, ca is the output (28) of the analogue frequency converter (2) via the gear unit (34) connected to the second input of the relaxation stage (10).

4. Analogue frequency converter according to Claim 2, ie? ti m e, that the time oscillator reference oscillator (21) is connected to another relaxation stage input (10).

An analog frequency converter according to Claim 2, characterized in that the threshold switch (9 ') is connected directly to the first input of the relaxation stage (30), and is connected via the gear unit stage (29) to the second input (D) of the relaxation stage ( 30).

6. Analog frequency converter Requirement 3 j 4, indicating that the first input (3 3) of the relaxation stage (10) is connected to the output of the threshold switch (9), with the second input (12) connected to the reference oscillator (23 ) or. over the gear unit stage (14) with the output (28) of the analogue frequency converter (2), and the threshold switch (9) is designed as a voltage comparator of a fixed threshold value (U).

An anaphogic frequency converter according to Claim 5, characterized in that, in the pcd assembly (5 '), the output of the threshold switch (9') is connected to the input of the gear unit stage (29) and the clock input of the D-trigger (303, and the output gear unit (29) is connected to the D-input of the D-trigger (30).

8. An analog frequency converter according to Claim 6, indicated to me that both inputs (11:12) and output (1?) Of the relaxation stage (10) are connected to three inputs of the first 1-gate (15) and to three the inverting inputs of the second I-gate (16) and the first I-gate (15) being connected to the exclusive output (37) for positive charge pulses and the second I-gate (36) to the negative input (18) for negative encoder charging pulses compensation charge (6).

An analog frequency converter according to claim 7, characterized in that the output of the threshold switch (9 ') is connected to the input of the first I-gate (31) and the inverting input of the second I-gate (32), that the output of the gear unit (29 ) connected to the further input of the first I-gate (31) and the output of the D-trigger (30) to the further inverting output of the second I-gate (32) and one I-gate (31) connected to the exclusive input for positive charging pulses (17) and the second I-gate (32) to the exclusive input for the negative charge pulses (18) of the compensation charge encoder (6).

An analog frequency converter according to claim 1 or one of claims 2 to 9, wherein the time base oscillator (21) is in the compensator encoder sub-assembly (6) whose output R is connected to the triggers (19; 20), and that the output (R) of the oscillator (23) is connected to the input of the gear unit (34).

33. An analog frequency converter according to Claims 3 to 3 0, according to variant I, n and radiated, that the output (U.) of the integrator (4)

A is connected to two further threshold switches (33,34), so that ευ outputs a threshold switch (33,34) connected via the OR gate (35) to the relaxation stage (36), the output (E) of the relaxation stage (36) is connected to one EXCLUSIVE-OR gate (39) input, and the gate (39) output is connected to the control input (3) of the multiplier (1) ·

Continued on the first side of the (P) polarity signal. The frequency of the polarity signal (P) is determined by the output frequency (F) of the analog frequency converter (2) or by the reference time oscillator (21). The control circuit (5) consists of a relaxation stage (10), a 1-circuit (15,16)) and a reduction stage (34). The compensation full encoder (6) contains constant current sources (24,25) which can be switched on via the flip-flop circuit (39,20) for the bands of one or more time-base oscillator periods (23). The additional circuit enables the processing of positive and negative currents (I).