SG95605A1 - Data processor system and instruction system using grouping - Google Patents

Data processor system and instruction system using grouping

Info

Publication number
SG95605A1
SG95605A1 SG9904821A SG1999004821A SG95605A1 SG 95605 A1 SG95605 A1 SG 95605A1 SG 9904821 A SG9904821 A SG 9904821A SG 1999004821 A SG1999004821 A SG 1999004821A SG 95605 A1 SG95605 A1 SG 95605A1
Authority
SG
Singapore
Prior art keywords
instruction
data processor
field
prefix
length
Prior art date
Application number
SG9904821A
Other languages
English (en)
Inventor
Svika Rozenshein
Jacob Tokar
Uri Dayan
Joe Paul Gergen
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of SG95605A1 publication Critical patent/SG95605A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
SG9904821A 1998-10-13 1999-09-24 Data processor system and instruction system using grouping SG95605A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/170,690 US6418527B1 (en) 1998-10-13 1998-10-13 Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods

Publications (1)

Publication Number Publication Date
SG95605A1 true SG95605A1 (en) 2003-04-23

Family

ID=22620876

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9904821A SG95605A1 (en) 1998-10-13 1999-09-24 Data processor system and instruction system using grouping

Country Status (10)

Country Link
US (1) US6418527B1 (fr)
EP (1) EP0994413B1 (fr)
JP (1) JP2000122864A (fr)
KR (1) KR100690225B1 (fr)
CN (1) CN1129843C (fr)
AT (1) ATE266226T1 (fr)
DE (1) DE69916962T2 (fr)
ES (1) ES2221282T3 (fr)
SG (1) SG95605A1 (fr)
TW (1) TW497073B (fr)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1039375A1 (fr) * 1999-03-19 2000-09-27 Motorola, Inc. Procédé et dispositif pour la mise en oeuvre des boucles a temps système zero
US6606700B1 (en) * 2000-02-26 2003-08-12 Qualcomm, Incorporated DSP with dual-mac processor and dual-mac coprocessor
WO2001067234A2 (fr) * 2000-03-08 2001-09-13 Sun Microsystems, Inc. Architecture de traitement d'ordinateur vliw possedant un nombre extensible de fichiers de registre
US6725360B1 (en) * 2000-03-31 2004-04-20 Intel Corporation Selectively processing different size data in multiplier and ALU paths in parallel
US7010788B1 (en) * 2000-05-19 2006-03-07 Hewlett-Packard Development Company, L.P. System for computing the optimal static schedule using the stored task execution costs with recent schedule execution costs
GB2366643B (en) 2000-05-25 2002-05-01 Siroyan Ltd Methods of compressing instructions for processors
US6415376B1 (en) * 2000-06-16 2002-07-02 Conexant Sytems, Inc. Apparatus and method for issue grouping of instructions in a VLIW processor
US6877084B1 (en) * 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode
KR20040064713A (ko) * 2001-11-26 2004-07-19 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 프로세서, 인스트럭션 세트, 인스트럭션 분배 방법 및컴파일링 방법
US7697946B2 (en) * 2002-06-04 2010-04-13 Forster Ian J Reflective communication using radio-frequency devices
JP3627725B2 (ja) * 2002-06-24 2005-03-09 セイコーエプソン株式会社 情報処理装置及び電子機器
US6944749B2 (en) * 2002-07-29 2005-09-13 Faraday Technology Corp. Method for quickly determining length of an execution package
US6865662B2 (en) * 2002-08-08 2005-03-08 Faraday Technology Corp. Controlling VLIW instruction operations supply to functional units using switches based on condition head field
WO2004114128A2 (fr) * 2003-06-25 2004-12-29 Koninklijke Philips Electronics N.V. Dispositif de traitement de donnees a commande par instructions
US7340588B2 (en) * 2003-11-24 2008-03-04 International Business Machines Corporation Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
US7873815B2 (en) 2004-03-04 2011-01-18 Qualcomm Incorporated Digital signal processors with configurable dual-MAC and dual-ALU
US20060149926A1 (en) * 2004-12-23 2006-07-06 Yuval Sapir Control words for instruction packets of processors and methods thereof
US20060149922A1 (en) * 2004-12-28 2006-07-06 Ceva D.S.P. Ltd. Multiple computational clusters in processors and methods thereof
US20060150171A1 (en) * 2004-12-28 2006-07-06 Ceva D.S.P. Ltd. Control words for instruction packets of processors and methods thereof
US7350040B2 (en) * 2005-03-03 2008-03-25 Microsoft Corporation Method and system for securing metadata to detect unauthorized access
US7526633B2 (en) * 2005-03-23 2009-04-28 Qualcomm Incorporated Method and system for encoding variable length packets with variable instruction sizes
US7793078B2 (en) * 2005-04-01 2010-09-07 Arm Limited Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding
JP5217431B2 (ja) * 2007-12-28 2013-06-19 富士通株式会社 演算処理装置及び演算処理装置の制御方法
US8285971B2 (en) * 2008-12-16 2012-10-09 International Business Machines Corporation Block driven computation with an address generation accelerator
US8458439B2 (en) * 2008-12-16 2013-06-04 International Business Machines Corporation Block driven computation using a caching policy specified in an operand data structure
US8407680B2 (en) * 2008-12-16 2013-03-26 International Business Machines Corporation Operand data structure for block computation
US8281106B2 (en) * 2008-12-16 2012-10-02 International Business Machines Corporation Specifying an addressing relationship in an operand data structure
US8327345B2 (en) * 2008-12-16 2012-12-04 International Business Machines Corporation Computation table for block computation
GB2565242B (en) 2010-12-24 2019-04-03 Qualcomm Technologies Int Ltd Encapsulated instruction set
GB2486737B (en) * 2010-12-24 2018-09-19 Qualcomm Technologies Int Ltd Instruction execution
WO2012131437A1 (fr) * 2011-03-30 2012-10-04 Freescale Semiconductor, Inc. Dispositif à circuit intégré et procédé pour permettre un accès inter-contexte
US8898433B2 (en) * 2012-04-26 2014-11-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Efficient extraction of execution sets from fetch sets
KR102210997B1 (ko) * 2014-03-12 2021-02-02 삼성전자주식회사 Vliw 명령어를 처리하는 방법 및 장치와 vliw 명령어를 처리하기 위한 명령어를 생성하는 방법 및 장치
US9940242B2 (en) * 2014-11-17 2018-04-10 International Business Machines Corporation Techniques for identifying instructions for decode-time instruction optimization grouping in view of cache boundaries
US9733940B2 (en) 2014-11-17 2017-08-15 International Business Machines Corporation Techniques for instruction group formation for decode-time instruction optimization based on feedback
US10402199B2 (en) 2015-10-22 2019-09-03 Texas Instruments Incorporated Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor
US20170192788A1 (en) * 2016-01-05 2017-07-06 Intel Corporation Binary translation support using processor instruction prefixes
CN107688854B (zh) * 2016-08-05 2021-10-19 中科寒武纪科技股份有限公司 一种能支持不同位宽运算数据的运算单元、方法及装置
US10761849B2 (en) * 2016-09-22 2020-09-01 Intel Corporation Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction
CN111813446A (zh) * 2019-04-12 2020-10-23 杭州中天微系统有限公司 一种数据加载和存储指令的处理方法和处理装置
JP2024516926A (ja) * 2022-01-26 2024-04-18 グーグル エルエルシー 可変長の命令を用いた並列復号命令セットコンピュータアーキテクチャ

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0220684A2 (fr) * 1985-10-25 1987-05-06 Hitachi, Ltd. Système de traitement de données
EP0455966A2 (fr) * 1990-05-10 1991-11-13 International Business Machines Corporation Processeur de prétraitement pour une antémémoire, capable de combiner des instructions
EP0500151A2 (fr) * 1985-11-08 1992-08-26 Nec Corporation Unité de commande de microprogramme
US5598544A (en) * 1990-10-20 1997-01-28 Fujitsu Limited Instruction buffer device for processing an instruction set of variable-length instruction codes

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0454985B1 (fr) * 1990-05-04 1996-12-18 International Business Machines Corporation Architecture de machine pour un jeu échelonnable d'instructions combinées
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
EP0651320B1 (fr) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Décodeur d'instructions superscalaires
DE69429061T2 (de) * 1993-10-29 2002-07-18 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
EP1186995B1 (fr) * 1993-11-05 2003-09-03 Intergraph Corporation Mémoire d'instructions avec commutateur crossbar associatif
DE69431998T2 (de) 1993-11-05 2004-08-05 Intergraph Hardware Technologies Co., Las Vegas Superskalare Rechnerarchitektur mit Softwarescheduling
US5630083A (en) * 1994-03-01 1997-05-13 Intel Corporation Decoder for decoding multiple instructions in parallel
US5822778A (en) * 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
JPH09265397A (ja) * 1996-03-29 1997-10-07 Hitachi Ltd Ｖｌｉｗ命令用プロセッサ
US6275927B2 (en) * 1998-09-21 2001-08-14 Advanced Micro Devices. Compressing variable-length instruction prefix bytes

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0220684A2 (fr) * 1985-10-25 1987-05-06 Hitachi, Ltd. Système de traitement de données
EP0500151A2 (fr) * 1985-11-08 1992-08-26 Nec Corporation Unité de commande de microprogramme
EP0455966A2 (fr) * 1990-05-10 1991-11-13 International Business Machines Corporation Processeur de prétraitement pour une antémémoire, capable de combiner des instructions
US5598544A (en) * 1990-10-20 1997-01-28 Fujitsu Limited Instruction buffer device for processing an instruction set of variable-length instruction codes

Also Published As

Publication number Publication date
ES2221282T3 (es) 2004-12-16
EP0994413A3 (fr) 2002-01-23
DE69916962D1 (de) 2004-06-09
CN1250906A (zh) 2000-04-19
DE69916962T2 (de) 2005-04-07
KR20000029005A (ko) 2000-05-25
US20020056035A1 (en) 2002-05-09
ATE266226T1 (de) 2004-05-15
CN1129843C (zh) 2003-12-03
EP0994413B1 (fr) 2004-05-06
KR100690225B1 (ko) 2007-03-12
TW497073B (en) 2002-08-01
EP0994413A2 (fr) 2000-04-19
JP2000122864A (ja) 2000-04-28
US6418527B1 (en) 2002-07-09

Similar Documents

Publication Publication Date Title
SG95605A1 (en) Data processor system and instruction system using grouping
IE851252L (en) Instruction prefetch system for conditional branch¹instruction for central processor unit
EP0911724A3 (fr) Procédé et méthode d' utilization de fichiers de registres
EP0651327A3 (fr) Recompilation des programmes pour une meilleure optimisation
EP0365188A3 (fr) Méthode et dispositif pour code de condition dans un processeur central
CA2029088A1 (fr) Mode d'enregistrement et d'execution d'instructions
BR9906952A (pt) Processo para facilitar uma programação de um dispositivo de controle, programa de software que está contido em um meio legìvel por computador para execução em um computador, respectivo dispositivo de controle, software objeto que está contido em um meio legìvel por computador em um site de internet, e, processo de habilitação de um usuário para personalizar o controle de um aparelho
CA2077273A1 (fr) Objets linguistiques neutres
WO2002035343A3 (fr) Procede et appareil d'instrumentation de logiciels
EP0674280A3 (fr) Mise en marche d'un logiciel après téléchargement de données créées par un logiciel.
AU5801294A (en) An apparatus for executing a plurality of program segments having different object code types in a single program or processor environment
EP1215569A4 (fr) Processeur de donnees
EP0871110A3 (fr) Prédiction de branchement dans une système d'ordinateur
GB2354615A (en) Computer processor with a replay system
EP1046995A3 (fr) Procédé et appareil faisant pour le débogage de code optimisé
HK1051729A1 (en) Method and processor for branch instruction
EP1004961A3 (fr) Méthode et système pour corréler des données de profil générées dynamiquement depuis un programme exécutable optimisé avec commandes de code source
EP0943995A3 (fr) Processeur ayant une insertion d'instruction externe en temps réel pour cause de débogage sans moniteur de débogage
EP0855648A3 (fr) Traitement de données avec exécution parallèle ou séquentielle d'instructions de programme
WO2007008880A3 (fr) Modification de chemin d'execution de code par redirection de mode noyau
WO2001044927A3 (fr) Procede et appareil pour effectuer une prelecture au niveau des fonctions
EP0893756A3 (fr) Procédé et appareil à commander l'exécution de branchement conditionnel dans un processeur
EP1109095A3 (fr) Circuit de pré-extraction d'instructions et prédiction de branchement
CA2240508A1 (fr) Traitement reparti
JPS5441039A (en) Processing unit of high level language program