CA2029088A1 - Mode d'enregistrement et d'execution d'instructions - Google Patents

Mode d'enregistrement et d'execution d'instructions

Info

Publication number
CA2029088A1
CA2029088A1 CA2029088A CA2029088A CA2029088A1 CA 2029088 A1 CA2029088 A1 CA 2029088A1 CA 2029088 A CA2029088 A CA 2029088A CA 2029088 A CA2029088 A CA 2029088A CA 2029088 A1 CA2029088 A1 CA 2029088A1
Authority
CA
Canada
Prior art keywords
instruction
specifying
execution system
instructing method
words
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2029088A
Other languages
English (en)
Other versions
CA2029088C (fr
Inventor
Takao Kato
Hideo Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CA2029088A1 publication Critical patent/CA2029088A1/fr
Application granted granted Critical
Publication of CA2029088C publication Critical patent/CA2029088C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
CA002029088A 1989-11-01 1990-10-31 Mode d'enregistrement et d'execution d'instructions Expired - Fee Related CA2029088C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-285471 1989-11-01
JP1285471A JP2835103B2 (ja) 1989-11-01 1989-11-01 命令指定方法及び命令実行方式

Publications (2)

Publication Number Publication Date
CA2029088A1 true CA2029088A1 (fr) 1991-05-02
CA2029088C CA2029088C (fr) 1994-05-03

Family

ID=17691950

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002029088A Expired - Fee Related CA2029088C (fr) 1989-11-01 1990-10-31 Mode d'enregistrement et d'execution d'instructions

Country Status (7)

Country Link
US (1) US5442762A (fr)
EP (1) EP0426393B1 (fr)
JP (1) JP2835103B2 (fr)
KR (1) KR930007041B1 (fr)
AU (1) AU625008B2 (fr)
CA (1) CA2029088C (fr)
DE (1) DE69031899T2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5745759A (en) * 1994-10-14 1998-04-28 Qnx Software Systems, Ltd. Window kernel
US6397262B1 (en) 1994-10-14 2002-05-28 Qnx Software Systems, Ltd. Window kernel

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
EP0547240B1 (fr) * 1991-07-08 2000-01-12 Seiko Epson Corporation Architecture risc de microprocesseur avec mode d'interruption et d'exception rapide
KR100299691B1 (ko) * 1991-07-08 2001-11-22 구사마 사부로 확장가능알아이에스씨마이크로프로세서구조
JP2746775B2 (ja) * 1991-08-05 1998-05-06 シャープ株式会社 中央処理装置
JPH05100897A (ja) * 1991-10-03 1993-04-23 Agency Of Ind Science & Technol 命令トレース方式
EP0551090B1 (fr) * 1992-01-06 1999-08-04 Hitachi, Ltd. Ordinateur possédant une capacité de traitement en parallèle
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
WO1994008287A1 (fr) 1992-09-29 1994-04-14 Seiko Epson Corporation Systeme et procede pour la gestion des operations de chargement et/ou de stockage dans un microprocesseur superscalaire
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994027216A1 (fr) * 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Systeme de couplage multiprocesseur a ordonnancement integre de la compilation et de l'execution assurant un traitement parallele
US6360313B1 (en) 1993-11-05 2002-03-19 Intergraph Corporation Instruction cache associative crossbar switch
DE69424370T2 (de) * 1993-11-05 2001-02-15 Intergraph Corp., Huntsville Befehlscachespeicher mit Kreuzschienenschalter
US5860085A (en) * 1994-08-01 1999-01-12 Cypress Semiconductor Corporation Instruction set for a content addressable memory array with read/write circuits and an interface register logic block
US5867726A (en) 1995-05-02 1999-02-02 Hitachi, Ltd. Microcomputer
JP2931890B2 (ja) 1995-07-12 1999-08-09 三菱電機株式会社 データ処理装置
US5848288A (en) * 1995-09-20 1998-12-08 Intel Corporation Method and apparatus for accommodating different issue width implementations of VLIW architectures
US5864704A (en) * 1995-10-10 1999-01-26 Chromatic Research, Inc. Multimedia processor using variable length instructions with opcode specification of source operand as result of prior instruction
JP3201716B2 (ja) * 1996-02-22 2001-08-27 シャープ株式会社 コンピュータ装置
US5867681A (en) * 1996-05-23 1999-02-02 Lsi Logic Corporation Microprocessor having register dependent immediate decompression
US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
US5794010A (en) * 1996-06-10 1998-08-11 Lsi Logic Corporation Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
US5890009A (en) * 1996-12-12 1999-03-30 International Business Machines Corporation VLIW architecture and method for expanding a parcel
JP3790607B2 (ja) 1997-06-16 2006-06-28 松下電器産業株式会社 Ｖｌｉｗプロセッサ
US6219779B1 (en) * 1997-06-16 2001-04-17 Matsushita Electric Industrial Co., Ltd. Constant reconstructing processor which supports reductions in code size
JP3412462B2 (ja) 1997-07-30 2003-06-03 松下電器産業株式会社 プロセッサ
JP3327818B2 (ja) * 1997-08-29 2002-09-24 松下電器産業株式会社 プログラム変換装置及び記録媒体
US6012138A (en) * 1997-12-19 2000-01-04 Lsi Logic Corporation Dynamically variable length CPU pipeline for efficiently executing two instruction sets
US6112299A (en) * 1997-12-31 2000-08-29 International Business Machines Corporation Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching
US6081884A (en) * 1998-01-05 2000-06-27 Advanced Micro Devices, Inc. Embedding two different instruction sets within a single long instruction word using predecode bits
US6076154A (en) * 1998-01-16 2000-06-13 U.S. Philips Corporation VLIW processor has different functional units operating on commands of different widths
EP0942357A3 (fr) 1998-03-11 2000-03-22 Matsushita Electric Industrial Co., Ltd. Microprocesseur compatible avec une pluralité de formats d'instructions
US6324639B1 (en) 1998-03-30 2001-11-27 Matsushita Electric Industrial Co., Ltd. Instruction converting apparatus using parallel execution code
US6237076B1 (en) * 1998-08-19 2001-05-22 International Business Machines Corporation Method for register renaming by copying a 32 bits instruction directly or indirectly to a 64 bits instruction
EP0992892B1 (fr) * 1998-10-06 2015-12-02 Texas Instruments Inc. Instructions d'accès de mémoire composées
US6681319B1 (en) 1998-10-06 2004-01-20 Texas Instruments Incorporated Dual access instruction and compound memory access instruction with compatible address fields
US6366998B1 (en) 1998-10-14 2002-04-02 Conexant Systems, Inc. Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model
US20070242074A1 (en) * 1999-04-09 2007-10-18 Dave Stuttard Parallel data processing apparatus
US20080162875A1 (en) * 1999-04-09 2008-07-03 Dave Stuttard Parallel Data Processing Apparatus
US8171263B2 (en) * 1999-04-09 2012-05-01 Rambus Inc. Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions
US7966475B2 (en) 1999-04-09 2011-06-21 Rambus Inc. Parallel data processing apparatus
US20080008393A1 (en) * 1999-04-09 2008-01-10 Dave Stuttard Parallel data processing apparatus
US8174530B2 (en) * 1999-04-09 2012-05-08 Rambus Inc. Parallel date processing apparatus
WO2000062182A2 (fr) 1999-04-09 2000-10-19 Clearspeed Technology Limited Appareil de traitement de donnees parallele
US8169440B2 (en) 1999-04-09 2012-05-01 Rambus Inc. Parallel data processing apparatus
US7802079B2 (en) 1999-04-09 2010-09-21 Clearspeed Technology Limited Parallel data processing apparatus
US7526630B2 (en) * 1999-04-09 2009-04-28 Clearspeed Technology, Plc Parallel data processing apparatus
US20080162874A1 (en) * 1999-04-09 2008-07-03 Dave Stuttard Parallel data processing apparatus
US8762691B2 (en) 1999-04-09 2014-06-24 Rambus Inc. Memory access consolidation for SIMD processing elements using transaction identifiers
US6928073B2 (en) * 1999-10-01 2005-08-09 Stmicroelectronics Ltd. Integrated circuit implementing packet transmission
US6675285B1 (en) * 2000-04-21 2004-01-06 Ati International, Srl Geometric engine including a computational module without memory contention
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
KR100636596B1 (ko) 2004-11-25 2006-10-23 한국전자통신연구원 고에너지 효율 병렬 처리 데이터 패스 구조
US8495341B2 (en) * 2010-02-17 2013-07-23 International Business Machines Corporation Instruction length based cracking for instruction of variable length storage operands
US9678754B2 (en) 2010-03-03 2017-06-13 Qualcomm Incorporated System and method of processing hierarchical very long instruction packets
US20110314263A1 (en) * 2010-06-22 2011-12-22 International Business Machines Corporation Instructions for performing an operation on two operands and subsequently storing an original value of operand
JP5625903B2 (ja) 2010-12-29 2014-11-19 富士通株式会社 演算処理装置および演算処理方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4488219A (en) * 1982-03-18 1984-12-11 International Business Machines Corporation Extended control word decoding
US4569016A (en) * 1983-06-30 1986-02-04 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
US5179680A (en) * 1987-04-20 1993-01-12 Digital Equipment Corporation Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus
US5036454A (en) * 1987-05-01 1991-07-30 Hewlett-Packard Company Horizontal computer having register multiconnect for execution of a loop with overlapped code
JP2635057B2 (ja) * 1987-11-04 1997-07-30 株式会社日立製作所 マイクロプロセッサ
US5115500A (en) * 1988-01-11 1992-05-19 International Business Machines Corporation Plural incompatible instruction format decode method and apparatus
US5202967A (en) * 1988-08-09 1993-04-13 Matsushita Electric Industrial Co., Ltd. Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction
US5051885A (en) * 1988-10-07 1991-09-24 Hewlett-Packard Company Data processing system for concurrent dispatch of instructions to multiple functional units
US5293592A (en) * 1989-04-07 1994-03-08 Intel Corporatino Decoder for pipelined system having portion indicating type of address generation and other portion controlling address generation within pipeline
US5197137A (en) * 1989-07-28 1993-03-23 International Business Machines Corporation Computer architecture for the concurrent execution of sequential programs

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5745759A (en) * 1994-10-14 1998-04-28 Qnx Software Systems, Ltd. Window kernel
US6397262B1 (en) 1994-10-14 2002-05-28 Qnx Software Systems, Ltd. Window kernel

Also Published As

Publication number Publication date
JP2835103B2 (ja) 1998-12-14
EP0426393A3 (en) 1991-08-07
CA2029088C (fr) 1994-05-03
JPH03147021A (ja) 1991-06-24
KR910010301A (ko) 1991-06-29
KR930007041B1 (ko) 1993-07-26
EP0426393B1 (fr) 1998-01-07
EP0426393A2 (fr) 1991-05-08
DE69031899D1 (de) 1998-02-12
US5442762A (en) 1995-08-15
DE69031899T2 (de) 1998-04-16
AU6572290A (en) 1991-08-01
AU625008B2 (en) 1992-06-25

Similar Documents

Publication Publication Date Title
CA2029088A1 (fr) Mode d'enregistrement et d'execution d'instructions
DE69031251D1 (de) Stromversorgungssteuerungssystem und -methode für einen Rechner
EP0840213A3 (fr) Procédé et dispositif pour l'exécution de branchements
DE69411430D1 (de) Prozesssteuerungssystemarchitektur
DE3750203D1 (de) Adaptives Prozessregelungssystem.
EP0457403A3 (en) Multilevel instruction cache, method for using said cache, method for compiling instructions for said cache and micro computer system using such a cache
DE3584718D1 (de) Bilddatenverarbeitungsverfahren und system dafuer.
AU6675390A (en) Data processing system with instruction tag apparatus
DE3787640D1 (de) Eingabeverfahren fuer eine datenverarbeitungsanlage.
DE68919248D1 (de) Prozessregelungssystem.
DE68924404D1 (de) System auswechselbarer Prallflächen.
DE68927513D1 (de) Prozessor für Prozessregelung
DE69414592D1 (de) Ausführung von datenverarbeitungsbefehlen
PL316532A1 (en) Data processing system and way of its operation
BR8506856A (pt) Processo de forja
DE69031992D1 (de) Steuerungssystem für die Ausführung von Befehlen
DE68924190D1 (de) Bildverarbeitungsmethode.
KR840006385A (ko) 매트릭스의 보강방법
DE58902718D1 (de) Prozessanlage.
DE3583973D1 (de) Informationsverarbeitungsanlage mit instruktionsvorabrufschaltung.
DE3763265D1 (de) Betriebssteuersystem und -verfahren.
DE3780335D1 (de) Prozesssteuerungssystem und -verfahren.
IL92605A0 (en) Production line method and apparatus for high performance instruction execution
BR8203994A (pt) Processo e matriz adaptada para trefilacao de arame
PL316566A1 (en) Data processing system and way of its operation

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed