SG77581A1 - Clock re-timing apparatus with cascaded delay stages - Google Patents

Clock re-timing apparatus with cascaded delay stages

Info

Publication number
SG77581A1
SG77581A1 SG1996010810A SG1996010810A SG77581A1 SG 77581 A1 SG77581 A1 SG 77581A1 SG 1996010810 A SG1996010810 A SG 1996010810A SG 1996010810 A SG1996010810 A SG 1996010810A SG 77581 A1 SG77581 A1 SG 77581A1
Authority
SG
Singapore
Prior art keywords
clock
delay stages
timing apparatus
cascaded delay
cascaded
Prior art date
Application number
SG1996010810A
Other languages
English (en)
Inventor
Mark Francis Rumreich
John William Gyurek
Original Assignee
Thomson Consumer Electronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Consumer Electronics filed Critical Thomson Consumer Electronics
Publication of SG77581A1 publication Critical patent/SG77581A1/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K6/00Manipulating pulses having a finite slope and not covered by one of the other main groups of this subclass
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/15046Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a tapped delay line
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/04Synchronising
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Picture Signal Circuits (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronizing For Television (AREA)
SG1996010810A 1995-10-25 1996-10-10 Clock re-timing apparatus with cascaded delay stages SG77581A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/547,830 US5663767A (en) 1995-10-25 1995-10-25 Clock re-timing apparatus with cascaded delay stages

Publications (1)

Publication Number Publication Date
SG77581A1 true SG77581A1 (en) 2001-01-16

Family

ID=24186322

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996010810A SG77581A1 (en) 1995-10-25 1996-10-10 Clock re-timing apparatus with cascaded delay stages

Country Status (8)

Country Link
US (1) US5663767A (fr)
EP (1) EP0771105B1 (fr)
JP (1) JP3370870B2 (fr)
KR (1) KR100397773B1 (fr)
CN (1) CN1155232C (fr)
MY (1) MY112993A (fr)
SG (1) SG77581A1 (fr)
TW (1) TW294877B (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5945862A (en) * 1997-07-31 1999-08-31 Rambus Incorporated Circuitry for the delay adjustment of a clock signal
KR100242972B1 (ko) * 1997-12-06 2000-02-01 윤종용 평판 디스플레이 장치의 트래킹 조정 회로
US5999032A (en) * 1998-03-05 1999-12-07 Etron Technology, Inc. Multiple phase synchronous race delay clock distribution circuit with skew compensation
US5923613A (en) * 1998-03-18 1999-07-13 Etron Technology, Inc. Latched type clock synchronizer with additional 180°-phase shift clock
US6111925A (en) * 1998-03-25 2000-08-29 Vanguard International Semiconductor Corporation Clock synchronized delay scheme using edge-triggered delay lines and latches with one clock lock time
US6150863A (en) * 1998-04-01 2000-11-21 Xilinx, Inc. User-controlled delay circuit for a programmable logic device
TW452731B (en) * 1998-05-29 2001-09-01 Amtran Technology Co Ltd Circuit that correctly transfers the analog image signal from VGA card to the digital image signal
CN1068167C (zh) * 1998-06-12 2001-07-04 瑞轩科技股份有限公司 用于视频图形信号的模拟/数字转换电路
US6369670B1 (en) * 1999-09-27 2002-04-09 Texas Instruments Incorporated Dynamically adjustable tapped delay line
US6580305B1 (en) * 1999-12-29 2003-06-17 Intel Corporation Generating a clock signal
FR2823341B1 (fr) * 2001-04-04 2003-07-25 St Microelectronics Sa Identification d'un circuit integre a partir de ses parametres physiques de fabrication
JP2014219963A (ja) * 2013-04-12 2014-11-20 信越ポリマー株式会社 センサーシート作製用シート及びその製造方法、タッチパッド用センサーシート及びその製造方法
CN104900260B (zh) * 2014-03-07 2018-08-24 中芯国际集成电路制造(上海)有限公司 延时选择器
KR102592124B1 (ko) 2018-09-21 2023-10-20 삼성전자주식회사 수평 동기화 신호에 기반하여 업 스케일링을 수행하는 시간 구간을 확장하기 위한 전자 장치 및 방법
CN112463125B (zh) * 2020-12-09 2023-09-15 百富计算机技术(深圳)有限公司 一种虚拟定时器的定时方法及设备

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059814A (ja) * 1983-09-12 1985-04-06 Hitachi Ltd プログラマブル遅延回路およびこれを用いた半導体集積回路装置
JPS60204121A (ja) * 1984-03-29 1985-10-15 Fujitsu Ltd 位相同期回路
US4667240A (en) * 1985-07-31 1987-05-19 Rca Corporation Timing correction circuitry as for TV signal recursive filters
US4638360A (en) * 1985-09-03 1987-01-20 Rca Corporation Timing correction for a picture-in-picture television system
US4814879A (en) * 1987-08-07 1989-03-21 Rca Licensing Corporation Signal phase alignment circuitry
US4782391A (en) * 1987-08-19 1988-11-01 Rca Licensing Corporation Multiple input digital video features processor for TV signals
US5031167A (en) * 1988-05-26 1991-07-09 Matsushita Electric Industrial Co., Ltd. Focus error detection system for an optical recording/reproducing system
US4992874A (en) * 1989-07-03 1991-02-12 Rca Licensing Corporation Method and apparatus for correcting timing errors as for a multi-picture display
JPH07142997A (ja) * 1990-11-29 1995-06-02 Internatl Business Mach Corp <Ibm> ディレイ・ライン較正回路
US5365128A (en) * 1991-10-17 1994-11-15 Intel Corporation High-resolution synchronous delay line
US5309111A (en) * 1992-06-26 1994-05-03 Thomson Consumer Electronics Apparatus for measuring skew timing errors
US5374860A (en) * 1993-01-15 1994-12-20 National Semiconductor Corporation Multi-tap digital delay line
US5532632A (en) * 1994-02-01 1996-07-02 Hughes Aircraft Company Method and circuit for synchronizing an input data stream with a sample clock
US5487095A (en) * 1994-06-17 1996-01-23 International Business Machines Corporation Edge detector

Also Published As

Publication number Publication date
CN1154624A (zh) 1997-07-16
KR970024572A (ko) 1997-05-30
CN1155232C (zh) 2004-06-23
MY112993A (en) 2001-10-31
KR100397773B1 (ko) 2003-11-20
TW294877B (en) 1997-01-01
JP3370870B2 (ja) 2003-01-27
JPH09149286A (ja) 1997-06-06
EP0771105B1 (fr) 2013-09-25
EP0771105A3 (fr) 1999-06-09
MX9605068A (es) 1997-09-30
US5663767A (en) 1997-09-02
EP0771105A2 (fr) 1997-05-02

Similar Documents

Publication Publication Date Title
GB2317282B (en) Input timing for semiconductor devices
GB2297854B (en) Real time clock
AU6339594A (en) Synchronized clock
GB2280555B (en) Clock recovery apparatus
SG77581A1 (en) Clock re-timing apparatus with cascaded delay stages
GB2217867B (en) Optical time delay apparatus
GB9408738D0 (en) Apparatus for reducing delays due to branches
GB2296166B (en) Clock synchronisation
EP0615360A3 (fr) Circuit de synchronisation d&#39;horloge.
GB9601348D0 (en) Clock synchronisation
GB2241946B (en) Delay device
GB2225462B (en) Input/output channel apparatus
GB2333385B (en) Variable clock apparatus
GB9401535D0 (en) Timing devices
GB2307994B (en) Clock
GB9519814D0 (en) Clock
GB9622934D0 (en) Clock multiplying apparatus using delay line loop circuitry
GB9322609D0 (en) Clock synchronisation
GB2268610B (en) Timing apparatus
GB2308206B (en) Clock
GB2301994B (en) Apparatus for minimizing clock skew
CA73449S (en) Clock
GB2285150B (en) Timing apparatus
ZA941364B (en) Time delay arrangement
GB9318117D0 (en) Clock