SG178691A1 - Method for manufacturing soi substrate - Google Patents

Method for manufacturing soi substrate Download PDF

Info

Publication number
SG178691A1
SG178691A1 SG2011059797A SG2011059797A SG178691A1 SG 178691 A1 SG178691 A1 SG 178691A1 SG 2011059797 A SG2011059797 A SG 2011059797A SG 2011059797 A SG2011059797 A SG 2011059797A SG 178691 A1 SG178691 A1 SG 178691A1
Authority
SG
Singapore
Prior art keywords
substrate
base substrate
semiconductor
heated
equal
Prior art date
Application number
SG2011059797A
Other languages
English (en)
Inventor
Komatsu Yoshihiro
Moriwaka Tomoaki
Original Assignee
Semiconductor Energy Lab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Lab filed Critical Semiconductor Energy Lab
Publication of SG178691A1 publication Critical patent/SG178691A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
SG2011059797A 2010-08-23 2011-08-18 Method for manufacturing soi substrate SG178691A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010186594 2010-08-23

Publications (1)

Publication Number Publication Date
SG178691A1 true SG178691A1 (en) 2012-03-29

Family

ID=45594394

Family Applications (2)

Application Number Title Priority Date Filing Date
SG2011059797A SG178691A1 (en) 2010-08-23 2011-08-18 Method for manufacturing soi substrate
SG2014010508A SG2014010508A (en) 2010-08-23 2011-08-18 Method for manufacturing soi substrate

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG2014010508A SG2014010508A (en) 2010-08-23 2011-08-18 Method for manufacturing soi substrate

Country Status (3)

Country Link
US (1) US20120045883A1 (https=)
JP (1) JP2012069927A (https=)
SG (2) SG178691A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6270450B2 (ja) * 2013-12-13 2018-01-31 キヤノン株式会社 放射線検出装置、放射線検出システム、及び、放射線検出装置の製造方法
US9299600B2 (en) * 2014-07-28 2016-03-29 United Microelectronics Corp. Method for repairing an oxide layer and method for manufacturing a semiconductor structure applying the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3501768B2 (ja) * 2001-04-18 2004-03-02 株式会社ガソニックス 基板熱処理装置およびフラットパネルデバイスの製造方法
JP4285244B2 (ja) * 2004-01-08 2009-06-24 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハの作製方法
JP2006080314A (ja) * 2004-09-09 2006-03-23 Canon Inc 結合基板の製造方法
FR2892230B1 (fr) * 2005-10-19 2008-07-04 Soitec Silicon On Insulator Traitement d'une couche de germamium
US7601271B2 (en) * 2005-11-28 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Process and equipment for bonding by molecular adhesion
US7763502B2 (en) * 2007-06-22 2010-07-27 Semiconductor Energy Laboratory Co., Ltd Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法

Also Published As

Publication number Publication date
SG2014010508A (en) 2014-05-29
US20120045883A1 (en) 2012-02-23
JP2012069927A (ja) 2012-04-05

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