SG173675A1 - General purpose protocol engine - Google Patents

General purpose protocol engine Download PDF

Info

Publication number
SG173675A1
SG173675A1 SG2011058336A SG2011058336A SG173675A1 SG 173675 A1 SG173675 A1 SG 173675A1 SG 2011058336 A SG2011058336 A SG 2011058336A SG 2011058336 A SG2011058336 A SG 2011058336A SG 173675 A1 SG173675 A1 SG 173675A1
Authority
SG
Singapore
Prior art keywords
protocol
data
definition
under test
device under
Prior art date
Application number
SG2011058336A
Other languages
English (en)
Inventor
George Conner
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of SG173675A1 publication Critical patent/SG173675A1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/03—Protocol definition or specification 

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
SG2011058336A 2009-03-13 2010-03-12 General purpose protocol engine SG173675A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/404,158 US8195419B2 (en) 2009-03-13 2009-03-13 General purpose protocol engine
PCT/US2010/027247 WO2010105238A2 (en) 2009-03-13 2010-03-12 General purpose protocol engine

Publications (1)

Publication Number Publication Date
SG173675A1 true SG173675A1 (en) 2011-09-29

Family

ID=42729156

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2011058336A SG173675A1 (en) 2009-03-13 2010-03-12 General purpose protocol engine

Country Status (8)

Country Link
US (2) US8195419B2 (https=)
EP (1) EP2406646B1 (https=)
JP (1) JP5260758B2 (https=)
KR (1) KR101297513B1 (https=)
CN (1) CN102341717B (https=)
MY (1) MY169817A (https=)
SG (1) SG173675A1 (https=)
WO (1) WO2010105238A2 (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201236395A (en) * 2011-02-23 2012-09-01 Novatek Microelectronics Corp TMDS receiver system and BIST method thereof
CN102655416A (zh) * 2011-03-04 2012-09-05 联咏科技股份有限公司 最小化传输差分信号接收器系统及其内建自我测试方法
US9521062B2 (en) * 2011-09-23 2016-12-13 Roche Diabetes Care, Inc. Communication test framework
US9910086B2 (en) 2012-01-17 2018-03-06 Allen Czamara Test IP-based A.T.E. instrument architecture
US9959186B2 (en) 2012-11-19 2018-05-01 Teradyne, Inc. Debugging in a semiconductor device test environment
US9116785B2 (en) * 2013-01-22 2015-08-25 Teradyne, Inc. Embedded tester
US10162007B2 (en) * 2013-02-21 2018-12-25 Advantest Corporation Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently
US20140236527A1 (en) * 2013-02-21 2014-08-21 Advantest Corporation Cloud based infrastructure for supporting protocol reconfigurations in protocol independent device testing systems
US10161993B2 (en) * 2013-02-21 2018-12-25 Advantest Corporation Tester with acceleration on memory and acceleration for automatic pattern generation within a FPGA block
EP2773068B1 (en) 2013-03-01 2019-04-10 Viavi Solutions Deutschland GmbH Test device and method
WO2015018455A1 (en) * 2013-08-09 2015-02-12 Advantest (Singapore) Pte. Ltd. Automated test equipment, instruction provider for providing a sequence of instructions, method for providing a signal to a device under test, method for providing a sequence of instructions and test system
US10288685B2 (en) * 2014-04-30 2019-05-14 Keysight Technologies, Inc. Multi-bank digital stimulus response in a single field programmable gate array
US9679098B2 (en) 2015-01-29 2017-06-13 Mentor Graphics Corporation Protocol probes
US10536553B1 (en) * 2015-09-04 2020-01-14 Cadence Design Systems, Inc. Method and system to transfer data between components of an emulation system
US9883412B2 (en) * 2016-01-04 2018-01-30 Microsoft Technology Licensing, Llc Verification of a wireless protocol implementation
US10481206B2 (en) * 2016-09-08 2019-11-19 Texas Instruments Incorporated Automatic test equipment (ATE) platform translation
US10976361B2 (en) 2018-12-20 2021-04-13 Advantest Corporation Automated test equipment (ATE) support framework for solid state device (SSD) odd sector sizes and protection modes
JP7101814B2 (ja) 2019-01-22 2022-07-15 株式会社アドバンテスト １または複数の被テストデバイスをテストするための自動試験装置、１または複数の被テストデバイスの自動試験のための方法、および、バッファメモリを使用するコンピュータプログラム
US11137910B2 (en) 2019-03-04 2021-10-05 Advantest Corporation Fast address to sector number/offset translation to support odd sector size testing
US11237202B2 (en) 2019-03-12 2022-02-01 Advantest Corporation Non-standard sector size system support for SSD testing
US10884847B1 (en) 2019-08-20 2021-01-05 Advantest Corporation Fast parallel CRC determination to support SSD testing
US11574248B2 (en) 2020-04-02 2023-02-07 Rovi Guides, Inc. Systems and methods for automated content curation using signature analysis
KR102440440B1 (ko) * 2020-12-16 2022-09-06 와이아이케이 주식회사 반도체 소자 검사 장치
TWI770855B (zh) * 2021-03-04 2022-07-11 凌華科技股份有限公司 裝置測試排序方法、裝置組態生成方法及其設備
WO2025154007A1 (en) * 2024-01-17 2025-07-24 Crea - Collaudi Elettronici Automatizzati S.R.L. Testing system and test method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6425101B1 (en) 1998-10-30 2002-07-23 Infineon Technologies North America Corp. Programmable JTAG network architecture to support proprietary debug protocol
US20030018457A1 (en) 2001-03-13 2003-01-23 Lett Gregory Scott Biological modeling utilizing image data
US7222261B2 (en) 2002-06-19 2007-05-22 Teradyne, Inc. Automatic test equipment for design-for-test (DFT) and built-in-self-test circuitry
US7181660B2 (en) * 2002-07-26 2007-02-20 Verigy Pte. Ltd. Reconstruction of non-deterministic algorithmic tester stimulus used as input to a device under test
US7216273B2 (en) 2003-06-26 2007-05-08 Teradyne, Inc. Method for testing non-deterministic device data
US7702767B2 (en) * 2004-03-09 2010-04-20 Jp Morgan Chase Bank User connectivity process management system
US7340166B1 (en) 2004-07-15 2008-03-04 Verizon Services Corp. Methods and apparatus for automated testing and analysis of dense wavelength division multiplexing (DWDM), wavelength selective and/or optical switching devices
KR100628835B1 (ko) 2005-02-26 2006-09-26 한국정보통신기술협회 시나리오 기반의 데이터 방송 수신기 시험 자동화 장치 및방법
US7233875B2 (en) * 2005-11-21 2007-06-19 Sigmatel, Inc. Test set for testing a device and methods for use therewith
US20090112548A1 (en) 2007-10-30 2009-04-30 Conner George W A method for testing in a reconfigurable tester
US20090113245A1 (en) 2007-10-30 2009-04-30 Teradyne, Inc. Protocol aware digital channel apparatus

Also Published As

Publication number Publication date
US20120221285A1 (en) 2012-08-30
JP5260758B2 (ja) 2013-08-14
US20100235135A1 (en) 2010-09-16
US8195419B2 (en) 2012-06-05
WO2010105238A3 (en) 2011-01-13
MY169817A (en) 2019-05-16
WO2010105238A2 (en) 2010-09-16
KR20120003886A (ko) 2012-01-11
CN102341717B (zh) 2013-09-11
CN102341717A (zh) 2012-02-01
EP2406646B1 (en) 2017-07-19
US8521465B2 (en) 2013-08-27
JP2012520471A (ja) 2012-09-06
KR101297513B1 (ko) 2013-08-16
EP2406646A2 (en) 2012-01-18
EP2406646A4 (en) 2014-08-06

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