SG148987A1 - Inter-connecting structure for semiconductor device package and method of the same - Google Patents

Inter-connecting structure for semiconductor device package and method of the same

Info

Publication number
SG148987A1
SG148987A1 SG200805063-5A SG2008050635A SG148987A1 SG 148987 A1 SG148987 A1 SG 148987A1 SG 2008050635 A SG2008050635 A SG 2008050635A SG 148987 A1 SG148987 A1 SG 148987A1
Authority
SG
Singapore
Prior art keywords
substrate
inter
semiconductor device
device package
same
Prior art date
Application number
SG200805063-5A
Other languages
English (en)
Inventor
Wen-Kun Yang
Diann-Fang Lin
Original Assignee
Advanced Chip Eng Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of SG148987A1 publication Critical patent/SG148987A1/en

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    • HELECTRICITY
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
SG200805063-5A 2007-07-06 2008-07-04 Inter-connecting structure for semiconductor device package and method of the same SG148987A1 (en)

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US8446243B2 (en) * 2008-10-31 2013-05-21 Infineon Technologies Austria Ag Method of constructing inductors and transformers
TW201131705A (en) * 2010-03-03 2011-09-16 Advanced Chip Eng Tech Inc Conductor package structure and method of the same
US20130214418A1 (en) * 2012-01-12 2013-08-22 King Dragon International Inc. Semiconductor Device Package with Slanting Structures
US20130181227A1 (en) * 2012-01-12 2013-07-18 King Dragon International Inc. LED Package with Slanting Structure and Method of the Same
CN102867759B (zh) * 2012-08-17 2015-04-29 日月光半导体制造股份有限公司 半导体封装构造及其制造方法
TWI492344B (zh) * 2013-04-09 2015-07-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9331038B2 (en) 2013-08-29 2016-05-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor interconnect structure
US9859265B2 (en) * 2014-06-06 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming the same
US10043769B2 (en) 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
KR102492733B1 (ko) 2017-09-29 2023-01-27 삼성디스플레이 주식회사 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법
US11404365B2 (en) * 2019-05-07 2022-08-02 International Business Machines Corporation Direct attachment of capacitors to flip chip dies

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US6069407A (en) * 1998-11-18 2000-05-30 Vlsi Technology, Inc. BGA package using PCB and tape in a die-up configuration
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6569712B2 (en) * 2001-10-19 2003-05-27 Via Technologies, Inc. Structure of a ball-grid array package substrate and processes for producing thereof
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
US20040088855A1 (en) * 2002-11-11 2004-05-13 Salman Akram Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods
US7309622B2 (en) * 2005-02-14 2007-12-18 Stats Chippac Ltd. Integrated circuit package system with heat sink
US20070096285A1 (en) * 2005-11-02 2007-05-03 Chin-Tien Chiu Semiconductor die package including construction for preventing delamination and/or cracking of the semiconductor die

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TWI344199B (en) 2011-06-21
KR20090004775A (ko) 2009-01-12
CN101339928A (zh) 2009-01-07
JP2009033153A (ja) 2009-02-12
CN101339928B (zh) 2011-04-06
TW200903763A (en) 2009-01-16
US20090008777A1 (en) 2009-01-08
DE102008031358A1 (de) 2009-01-08

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