SG144700A1 - A method, apparatus, and instruction for performing a sign operation that multiplies - Google Patents
A method, apparatus, and instruction for performing a sign operation that multipliesInfo
- Publication number
- SG144700A1 SG144700A1 SG200307424-2A SG2003074242A SG144700A1 SG 144700 A1 SG144700 A1 SG 144700A1 SG 2003074242 A SG2003074242 A SG 2003074242A SG 144700 A1 SG144700 A1 SG 144700A1
- Authority
- SG
- Singapore
- Prior art keywords
- instruction
- sign
- multiplies
- source operand
- sign operation
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3812—Devices capable of handling different types of numbers
- G06F2207/382—Reconfigurable for different fixed word lengths
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/610,929 US7539714B2 (en) | 2003-06-30 | 2003-06-30 | Method, apparatus, and instruction for performing a sign operation that multiplies |
Publications (1)
Publication Number | Publication Date |
---|---|
SG144700A1 true SG144700A1 (en) | 2008-08-28 |
Family
ID=33452633
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200307424-2A SG144700A1 (en) | 2003-06-30 | 2003-12-17 | A method, apparatus, and instruction for performing a sign operation that multiplies |
Country Status (10)
Country | Link |
---|---|
US (1) | US7539714B2 (ru) |
EP (2) | EP2284694B1 (ru) |
JP (1) | JP4869552B2 (ru) |
KR (1) | KR100841131B1 (ru) |
CN (1) | CN1577249B (ru) |
BR (2) | BR0306094A (ru) |
MX (1) | MXPA03011899A (ru) |
RU (1) | RU2275677C2 (ru) |
SG (1) | SG144700A1 (ru) |
TW (1) | TWI305882B (ru) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7424501B2 (en) * | 2003-06-30 | 2008-09-09 | Intel Corporation | Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations |
CN101421935B (zh) * | 2004-09-20 | 2011-05-25 | Divx公司 | 视频去块滤波器 |
US7475103B2 (en) | 2005-03-17 | 2009-01-06 | Qualcomm Incorporated | Efficient check node message transform approximation for LDPC decoder |
US7747088B2 (en) * | 2005-09-28 | 2010-06-29 | Arc International (Uk) Limited | System and methods for performing deblocking in microprocessor-based video codec applications |
US20080071851A1 (en) * | 2006-09-20 | 2008-03-20 | Ronen Zohar | Instruction and logic for performing a dot-product operation |
US20090113174A1 (en) * | 2007-10-31 | 2009-04-30 | Texas Instruments Incorporated | Sign Operation Instructions and Circuitry |
US8515052B2 (en) | 2007-12-17 | 2013-08-20 | Wai Wu | Parallel signal processing system and method |
US8041927B2 (en) * | 2008-04-16 | 2011-10-18 | Nec Corporation | Processor apparatus and method of processing multiple data by single instructions |
CN102132338B (zh) * | 2008-10-24 | 2013-06-19 | 夏普株式会社 | 显示装置和显示装置的驱动方法 |
US9747105B2 (en) * | 2009-12-17 | 2017-08-29 | Intel Corporation | Method and apparatus for performing a shift and exclusive or operation in a single instruction |
US9003170B2 (en) * | 2009-12-22 | 2015-04-07 | Intel Corporation | Bit range isolation instructions, methods, and apparatus |
KR101924885B1 (ko) * | 2010-07-14 | 2018-12-04 | 가부시키가이샤 엔.티.티.도코모 | 비디오 코딩을 위한 저 복잡성 인트라 예측 |
RU2467377C1 (ru) * | 2011-04-19 | 2012-11-20 | ОАО "Концерн "Моринформсистема-Агат" | Способ и устройство умножения чисел в коде "1 из 4" |
RU2461867C1 (ru) * | 2011-06-23 | 2012-09-20 | Российская Федерация, от имени которой выступает Государственная корпорация по атомной энергии "Росатом" - Госкорпорация "Росатом" | Реконфигурируемый вычислительный конвейер |
WO2013095601A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Instruction for element offset calculation in a multi-dimensional array |
US9715383B2 (en) | 2012-03-15 | 2017-07-25 | International Business Machines Corporation | Vector find element equal instruction |
US9459868B2 (en) | 2012-03-15 | 2016-10-04 | International Business Machines Corporation | Instruction to load data up to a dynamically determined memory boundary |
US9710266B2 (en) * | 2012-03-15 | 2017-07-18 | International Business Machines Corporation | Instruction to compute the distance to a specified memory boundary |
US9459867B2 (en) | 2012-03-15 | 2016-10-04 | International Business Machines Corporation | Instruction to load data up to a specified memory boundary indicated by the instruction |
US9501276B2 (en) * | 2012-12-31 | 2016-11-22 | Intel Corporation | Instructions and logic to vectorize conditional loops |
US9207941B2 (en) * | 2013-03-15 | 2015-12-08 | Intel Corporation | Systems, apparatuses, and methods for reducing the number of short integer multiplications |
CN103995475B (zh) * | 2014-05-16 | 2016-05-18 | 北京航空航天大学 | 一种柔性嵌入式被测设备模拟器 |
US20160125263A1 (en) | 2014-11-03 | 2016-05-05 | Texas Instruments Incorporated | Method to compute sliding window block sum using instruction based selective horizontal addition in vector processor |
US10346944B2 (en) | 2017-04-09 | 2019-07-09 | Intel Corporation | Machine learning sparse computation mechanism |
CN108733347B (zh) * | 2017-04-20 | 2021-01-29 | 杭州海康威视数字技术股份有限公司 | 一种数据处理方法及装置 |
RU2653310C1 (ru) * | 2017-05-24 | 2018-05-07 | федеральное государственное бюджетное образовательное учреждение высшего образования "Воронежский государственный университет" (ФГБОУ ВО "ВГУ") | Устройство для умножения числа по модулю на константу |
CN107807819B (zh) * | 2017-07-20 | 2021-06-25 | 上海寒武纪信息科技有限公司 | 一种支持离散数据表示的用于执行人工神经网络正向运算的装置及方法 |
RU2666285C1 (ru) * | 2017-10-06 | 2018-09-06 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Вятский государственный университет" (ВятГУ) | Способ организации выполнения операции умножения двух чисел в модулярно-логарифмическом формате представления с плавающей точкой на гибридных многоядерных процессорах |
US11614920B2 (en) * | 2020-05-07 | 2023-03-28 | Meta Platforms, Inc. | Bypassing zero-value multiplications in a hardware multiplier |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5128890A (en) * | 1991-05-06 | 1992-07-07 | Motorola, Inc. | Apparatus for performing multiplications with reduced power and a method therefor |
US6038583A (en) * | 1997-10-23 | 2000-03-14 | Advanced Micro Devices, Inc. | Method and apparatus for simultaneously multiplying two or more independent pairs of operands and calculating a rounded products |
US6243803B1 (en) * | 1998-03-31 | 2001-06-05 | Intel Corporation | Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry |
US6292814B1 (en) * | 1998-06-26 | 2001-09-18 | Hitachi America, Ltd. | Methods and apparatus for implementing a sign function |
US6490607B1 (en) * | 1998-01-28 | 2002-12-03 | Advanced Micro Devices, Inc. | Shared FP and SIMD 3D multiplier |
Family Cites Families (9)
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FR1398092A (fr) * | 1964-03-26 | 1965-05-07 | Saint Gobain | Nouveau circuit électronique de commutation |
FR1509926A (fr) * | 1966-03-21 | 1968-01-19 | Saint Gobain Techn Nouvelles | Circuit multiplicateur scalaire |
JPS63310023A (ja) * | 1987-06-11 | 1988-12-19 | Matsushita Electric Ind Co Ltd | 符号付固定小数点乗算装置 |
NL9001608A (nl) * | 1990-07-16 | 1992-02-17 | Philips Nv | Ontvanger voor meerwaardige digitale signalen. |
JPH04155503A (ja) * | 1990-10-19 | 1992-05-28 | Matsushita Electric Ind Co Ltd | ニューロ制御装置 |
US5349545A (en) * | 1992-11-24 | 1994-09-20 | Intel Corporation | Arithmetic logic unit dequantization |
US6023489A (en) * | 1995-05-24 | 2000-02-08 | Leica Geosystems Inc. | Method and apparatus for code synchronization in a global positioning system receiver |
US6351293B1 (en) * | 1998-05-18 | 2002-02-26 | Sarnoff Corporation | Decision directed phase detector |
US6397240B1 (en) * | 1999-02-18 | 2002-05-28 | Agere Systems Guardian Corp. | Programmable accelerator for a programmable processor system |
-
2003
- 2003-06-30 US US10/610,929 patent/US7539714B2/en active Active
- 2003-10-13 TW TW092128278A patent/TWI305882B/zh not_active IP Right Cessation
- 2003-12-17 SG SG200307424-2A patent/SG144700A1/en unknown
- 2003-12-18 MX MXPA03011899A patent/MXPA03011899A/es not_active Application Discontinuation
- 2003-12-22 JP JP2003425712A patent/JP4869552B2/ja not_active Expired - Fee Related
- 2003-12-25 RU RU2003137709/09A patent/RU2275677C2/ru not_active IP Right Cessation
- 2003-12-25 CN CN2003101130822A patent/CN1577249B/zh not_active Expired - Fee Related
- 2003-12-29 BR BR0306094-2A patent/BR0306094A/pt not_active IP Right Cessation
- 2003-12-29 BR BRPI0306094-2A patent/BRPI0306094B1/pt unknown
- 2003-12-29 EP EP10184624.4A patent/EP2284694B1/en not_active Expired - Lifetime
- 2003-12-29 EP EP03258226A patent/EP1496432A3/en not_active Ceased
- 2003-12-30 KR KR1020030099839A patent/KR100841131B1/ko not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5128890A (en) * | 1991-05-06 | 1992-07-07 | Motorola, Inc. | Apparatus for performing multiplications with reduced power and a method therefor |
US6038583A (en) * | 1997-10-23 | 2000-03-14 | Advanced Micro Devices, Inc. | Method and apparatus for simultaneously multiplying two or more independent pairs of operands and calculating a rounded products |
US6490607B1 (en) * | 1998-01-28 | 2002-12-03 | Advanced Micro Devices, Inc. | Shared FP and SIMD 3D multiplier |
US6243803B1 (en) * | 1998-03-31 | 2001-06-05 | Intel Corporation | Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry |
US6292814B1 (en) * | 1998-06-26 | 2001-09-18 | Hitachi America, Ltd. | Methods and apparatus for implementing a sign function |
Also Published As
Publication number | Publication date |
---|---|
CN1577249B (zh) | 2010-04-14 |
US20040267858A1 (en) | 2004-12-30 |
EP1496432A2 (en) | 2005-01-12 |
CN1577249A (zh) | 2005-02-09 |
EP1496432A3 (en) | 2007-12-12 |
RU2275677C2 (ru) | 2006-04-27 |
BRPI0306094B1 (pt) | 2017-06-27 |
TWI305882B (en) | 2009-02-01 |
JP4869552B2 (ja) | 2012-02-08 |
KR20050005729A (ko) | 2005-01-14 |
RU2003137709A (ru) | 2005-06-10 |
US7539714B2 (en) | 2009-05-26 |
KR100841131B1 (ko) | 2008-06-24 |
MXPA03011899A (es) | 2005-01-13 |
EP2284694B1 (en) | 2013-05-15 |
JP2005025719A (ja) | 2005-01-27 |
TW200500878A (en) | 2005-01-01 |
EP2284694A1 (en) | 2011-02-16 |
BR0306094A (pt) | 2005-05-17 |
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