JP4869552B2 - 符号乗算処理を実行する方法及び装置 - Google Patents
符号乗算処理を実行する方法及び装置 Download PDFInfo
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Description
(Compact Flash)カードコントロール149、液晶(LCD)コントロール150、DMA(Direct Memory Access)コントローラ151、及び代替バスマスタインタフェース152を含む他の様々なシステム装置と通信するためのバス141に接続される。一実施例では、データ処理システム140はまた、I/Oバス153を介し様々なI/O装置と通信するためのI/Oブリッジ154を備える。このようなI/O装置は、以下に限定されるものではないが、例えば、UART(Universal Asynchronous Receiver/Transmitter)155、USB156、ブルートゥース無線UART157、及びI/O拡張インタフェース158から構成されてもよい。
ここで、アレイB1014とC1022の補正係数が、アップダウンランプ(updown ramp)
d1=SIGN(d)×(MAX(0, ABS(d)−MAX(0, 2×(ABS(d)−strength))))
により計算される。
d2=clipd1((A−D)/4, d1/2)
により計算される。
B’=clip(B+d1) C’=clip(C−d1)
補正される。
A’=A−d2 D’=D+d2
補正される。
最大値=MAX(V1 V2 V3 V4 V5 V6 V7 V8)
最小値=MIN(V1 V2 V3 V4 V5 V6 V7 V8)
特徴付けされる。
a3,0=(2×V3−5×V4+5×V5−2×V6)/8
a3,1=(2×V1−5×V2+5×V3−2×V4)/8
a3,2=(2×V5−5×V6+5×V7−2×V8)/8
a3,0’=SIGN(a3,0)×MIN(ABS(a3,0), ABS(a3,1), ABS(a3,2))
d=CLIP(5×(a3,0’−a3,0)/8, 0, ((V4−V5)/2×δ(ABS(a3,0)<量子化係数))
計算される。ただし、δ()は、真の場合には1、偽の場合には0と評価する。
m<1の場合、ABS(V1−V0)<QPのとき、pm=V0とし、そうでないときpm=V1とする。
102、166、200 プロセッサ
104、167 キャッシュ
106、145、164 レジスタファイル
108、142、162 実行ユニット
109、143,163 命令セット
110 プロセッサバス
112 グラフィックス/ビデオカード
114 AGPインターコネクト
116 メモリコントローラハブ(MCH)
118 メモリインタフェース
120 メモリ
122 専用ハブインタフェースバス
124 データ記憶装置
126 無線送信機
128 フラッシュBIOS
130 I/Oコントローラハブ(ICH)
134 ネットワークコントローラ
141 バス
144、165 デコーダ
146 SDRAMコントロール
147 SRAMコントロール
148 バーストフラッシュメモリインタフェース
149 PCMCIA/CFカードコントロール
150 LCDコントロール
151 DMAコントロール
152 代替バスマスタインタフェース
153 I/Oバス
154 I/Oブリッジ
155 UART
156 USB
157 ブルートゥースUART
158 I/O拡張インタフェース
159 処理コア
161 SIMDコプロセッサ
168 I/Oシステム
169 無線インタフェース
201 フロントエンド
202 高速スケジューラ
203 アウト・オブ・オーダーエンジン
204 低速/通常浮動小数点スケジューラ
206 シンプル浮動小数点スケジューラ
211 実行ブロック
212、214 アドレス生成ユニット(AGU)
216、218 高速ALU
220 低速ALU
222 浮動小数点ALU
224 浮動小数点移動ユニット
226 命令プリフェッチャ
228 命令デコーダ
230 トレースキャッシュ
232 マイクロコードROM
234 uopキュー
430 符号計算論理
600、650 回路
606、608 2−入力(2:1)マルチプレクサ(mux)
614 加算器
618 3−入力(3:1)マルチプレクサ(mux)
624 ゼロ検出回路
628 論理NORゲート
920 絶対値計算論理
Claims (4)
- 格納領域と、
該格納領域に接続される実行リソースと、
を有するプロセッサを含む装置であって、
前記実行リソースは、第1オペランドと第2オペランドとを含む第1命令を実行し、該第1命令に応答して、前記第2オペランドが正の値である場合には前記第1オペランドの値を、前記第2オペランドがゼロの値である場合にはゼロの値を、前記第2オペランドが負の値である場合には前記第1オペランドの反対の符号の値を有する結果を前記格納領域に格納することを特徴とする装置。 - Packedデータ要素を格納できるレジスタファイルと、
前記レジスタファイルに接続され、複数のPackedデータ命令に応答して前記レジスタファイルに値を格納する実行ユニットと、
を有するプロセッサであって、
前記実行ユニットは、複数の結果データ要素から構成される結果を前記レジスタファイルに格納することにより前記複数のPackedデータ命令の第1命令に応答し、
前記複数の結果データ要素の各々は、複数の第1ソースデータ要素と複数の第2ソースデータ要素の各自の値に対して、前記複数の第2ソースデータ要素の対応する第2ソースデータ要素の「1」,「0」又は「−1」の符号の値と乗算された前記複数の第1ソースデータ要素の対応する第1ソースデータ要素に等しいことを特徴とするプロセッサ。 - フロントエンドによって、第1オペランド符号と第1オペランド量を有する第1オペランドと第2オペランド符号と第2オペランド量を有する第2オペランドとを特定する命令をフェッチするステップと、
実行ユニットを使用して、入力された前記第2オペランドが正であるか判断し、そのとき前記命令に応答して前記第1オペランドを結果として格納し、前記第2オペランドが負であるか判断し、そのとき前記第1オペランドと「−1」との積に等しい値を前記命令の結果として格納し、前記第2オペランドがゼロであるか判断し、そのときゼロを前記命令の結果として格納するステップと、
を有することを特徴とする方法。 - 第1Packedデータ命令と、複数の第1ソースデータ要素から構成される第1Packedデータと、複数の第2ソースデータ要素から構成される第2Packedデータとを格納するメモリと、
前記第1Packedデータ命令を実行し、複数の結果Packedデータ要素から構成される結果Packedデータをプロセッサ格納領域に格納するプロセッサと、
を有するシステムであって、
前記複数の第2ソースデータ要素の非ゼロ要素に対応する前記複数の結果Packedデータ要素のそれぞれは、前記複数の第1ソースデータ要素と前記複数の第2ソースデータ要素との対応する要素の双方の符号により決定される符号と、前記複数の第2ソースデータ要素の対応する要素のすべての非ゼロの値に対する前記複数の第1Packedデータ要素の対応する要素の大きさとを有することを特徴とするシステム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/610,929 US7539714B2 (en) | 2003-06-30 | 2003-06-30 | Method, apparatus, and instruction for performing a sign operation that multiplies |
US610929 | 2003-06-30 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005025719A JP2005025719A (ja) | 2005-01-27 |
JP2005025719A5 JP2005025719A5 (ja) | 2007-02-01 |
JP4869552B2 true JP4869552B2 (ja) | 2012-02-08 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003425712A Expired - Fee Related JP4869552B2 (ja) | 2003-06-30 | 2003-12-22 | 符号乗算処理を実行する方法及び装置 |
Country Status (10)
Country | Link |
---|---|
US (1) | US7539714B2 (ja) |
EP (2) | EP2284694B1 (ja) |
JP (1) | JP4869552B2 (ja) |
KR (1) | KR100841131B1 (ja) |
CN (1) | CN1577249B (ja) |
BR (2) | BRPI0306094B1 (ja) |
MX (1) | MXPA03011899A (ja) |
RU (1) | RU2275677C2 (ja) |
SG (1) | SG144700A1 (ja) |
TW (1) | TWI305882B (ja) |
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RU2666285C1 (ru) * | 2017-10-06 | 2018-09-06 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Вятский государственный университет" (ВятГУ) | Способ организации выполнения операции умножения двух чисел в модулярно-логарифмическом формате представления с плавающей точкой на гибридных многоядерных процессорах |
US11614920B2 (en) * | 2020-05-07 | 2023-03-28 | Meta Platforms, Inc. | Bypassing zero-value multiplications in a hardware multiplier |
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NL9001608A (nl) * | 1990-07-16 | 1992-02-17 | Philips Nv | Ontvanger voor meerwaardige digitale signalen. |
JPH04155503A (ja) * | 1990-10-19 | 1992-05-28 | Matsushita Electric Ind Co Ltd | ニューロ制御装置 |
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US6038583A (en) * | 1997-10-23 | 2000-03-14 | Advanced Micro Devices, Inc. | Method and apparatus for simultaneously multiplying two or more independent pairs of operands and calculating a rounded products |
US6490607B1 (en) * | 1998-01-28 | 2002-12-03 | Advanced Micro Devices, Inc. | Shared FP and SIMD 3D multiplier |
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US6292814B1 (en) * | 1998-06-26 | 2001-09-18 | Hitachi America, Ltd. | Methods and apparatus for implementing a sign function |
US6397240B1 (en) * | 1999-02-18 | 2002-05-28 | Agere Systems Guardian Corp. | Programmable accelerator for a programmable processor system |
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- 2003-10-13 TW TW092128278A patent/TWI305882B/zh not_active IP Right Cessation
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EP1496432A2 (en) | 2005-01-12 |
BR0306094A (pt) | 2005-05-17 |
EP2284694A1 (en) | 2011-02-16 |
EP1496432A3 (en) | 2007-12-12 |
SG144700A1 (en) | 2008-08-28 |
TW200500878A (en) | 2005-01-01 |
BRPI0306094B1 (pt) | 2017-06-27 |
MXPA03011899A (es) | 2005-01-13 |
US7539714B2 (en) | 2009-05-26 |
CN1577249A (zh) | 2005-02-09 |
JP2005025719A (ja) | 2005-01-27 |
RU2003137709A (ru) | 2005-06-10 |
KR20050005729A (ko) | 2005-01-14 |
KR100841131B1 (ko) | 2008-06-24 |
EP2284694B1 (en) | 2013-05-15 |
RU2275677C2 (ru) | 2006-04-27 |
CN1577249B (zh) | 2010-04-14 |
TWI305882B (en) | 2009-02-01 |
US20040267858A1 (en) | 2004-12-30 |
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