SG129307A1 - Shared translation address caching - Google Patents

Shared translation address caching

Info

Publication number
SG129307A1
SG129307A1 SG200502827A SG200502827A SG129307A1 SG 129307 A1 SG129307 A1 SG 129307A1 SG 200502827 A SG200502827 A SG 200502827A SG 200502827 A SG200502827 A SG 200502827A SG 129307 A1 SG129307 A1 SG 129307A1
Authority
SG
Singapore
Prior art keywords
translation address
address caching
shared translation
shared
caching
Prior art date
Application number
SG200502827A
Other languages
English (en)
Inventor
Bryan White
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG129307A1 publication Critical patent/SG129307A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Computer Graphics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Digital Computer Display Output (AREA)
  • Image Generation (AREA)
SG200502827A 2000-09-29 2001-09-26 Shared translation address caching SG129307A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/676,844 US6859208B1 (en) 2000-09-29 2000-09-29 Shared translation address caching

Publications (1)

Publication Number Publication Date
SG129307A1 true SG129307A1 (en) 2007-02-26

Family

ID=24716246

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200502827A SG129307A1 (en) 2000-09-29 2001-09-26 Shared translation address caching

Country Status (11)

Country Link
US (2) US6859208B1 (ko)
EP (1) EP1325417B1 (ko)
JP (1) JP3810736B2 (ko)
KR (1) KR100571730B1 (ko)
CN (1) CN1503945B (ko)
AU (1) AU2001294840A1 (ko)
DE (1) DE60142841D1 (ko)
HK (1) HK1053716A1 (ko)
SG (1) SG129307A1 (ko)
TW (1) TW576967B (ko)
WO (1) WO2002027499A2 (ko)

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JP5076317B2 (ja) * 2005-12-27 2012-11-21 ソニー株式会社 情報処理装置、情報処理方法及びそのプログラム
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US8347064B1 (en) 2006-09-19 2013-01-01 Nvidia Corporation Memory access techniques in an aperture mapped memory space
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US8700883B1 (en) 2006-10-24 2014-04-15 Nvidia Corporation Memory access techniques providing for override of a page table
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US8504794B1 (en) 2006-11-01 2013-08-06 Nvidia Corporation Override system and method for memory access management
US8706975B1 (en) 2006-11-01 2014-04-22 Nvidia Corporation Memory access management block bind system and method
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Also Published As

Publication number Publication date
HK1053716A1 (en) 2003-10-31
JP3810736B2 (ja) 2006-08-16
AU2001294840A1 (en) 2002-04-08
WO2002027499A3 (en) 2003-03-13
US6859208B1 (en) 2005-02-22
KR20030034224A (ko) 2003-05-01
WO2002027499A2 (en) 2002-04-04
TW576967B (en) 2004-02-21
JP2004510250A (ja) 2004-04-02
CN1503945B (zh) 2010-04-28
DE60142841D1 (de) 2010-09-30
CN1503945A (zh) 2004-06-09
US20050122340A1 (en) 2005-06-09
US7145568B2 (en) 2006-12-05
KR100571730B1 (ko) 2006-04-18
EP1325417B1 (en) 2010-08-18
EP1325417A2 (en) 2003-07-09

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