AU2001294840A1 - Shared translation address caching - Google Patents

Shared translation address caching

Info

Publication number
AU2001294840A1
AU2001294840A1 AU2001294840A AU9484001A AU2001294840A1 AU 2001294840 A1 AU2001294840 A1 AU 2001294840A1 AU 2001294840 A AU2001294840 A AU 2001294840A AU 9484001 A AU9484001 A AU 9484001A AU 2001294840 A1 AU2001294840 A1 AU 2001294840A1
Authority
AU
Australia
Prior art keywords
translation address
address caching
shared translation
shared
caching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001294840A
Inventor
Bryan White
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001294840A1 publication Critical patent/AU2001294840A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
AU2001294840A 2000-09-29 2001-09-26 Shared translation address caching Abandoned AU2001294840A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/676,844 US6859208B1 (en) 2000-09-29 2000-09-29 Shared translation address caching
US09/676,844 2000-09-29
PCT/US2001/030362 WO2002027499A2 (en) 2000-09-29 2001-09-26 Shared translation address caching

Publications (1)

Publication Number Publication Date
AU2001294840A1 true AU2001294840A1 (en) 2002-04-08

Family

ID=24716246

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001294840A Abandoned AU2001294840A1 (en) 2000-09-29 2001-09-26 Shared translation address caching

Country Status (11)

Country Link
US (2) US6859208B1 (en)
EP (1) EP1325417B1 (en)
JP (1) JP3810736B2 (en)
KR (1) KR100571730B1 (en)
CN (1) CN1503945B (en)
AU (1) AU2001294840A1 (en)
DE (1) DE60142841D1 (en)
HK (1) HK1053716A1 (en)
SG (1) SG129307A1 (en)
TW (1) TW576967B (en)
WO (1) WO2002027499A2 (en)

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JP5076317B2 (en) * 2005-12-27 2012-11-21 ソニー株式会社 Information processing apparatus, information processing method, and program thereof
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Also Published As

Publication number Publication date
WO2002027499A2 (en) 2002-04-04
KR100571730B1 (en) 2006-04-18
CN1503945A (en) 2004-06-09
KR20030034224A (en) 2003-05-01
WO2002027499A3 (en) 2003-03-13
JP2004510250A (en) 2004-04-02
HK1053716A1 (en) 2003-10-31
EP1325417A2 (en) 2003-07-09
SG129307A1 (en) 2007-02-26
US6859208B1 (en) 2005-02-22
CN1503945B (en) 2010-04-28
US7145568B2 (en) 2006-12-05
EP1325417B1 (en) 2010-08-18
DE60142841D1 (en) 2010-09-30
TW576967B (en) 2004-02-21
US20050122340A1 (en) 2005-06-09
JP3810736B2 (en) 2006-08-16

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