SG128451A1 - Improved etch stop layer - Google Patents
Improved etch stop layerInfo
- Publication number
- SG128451A1 SG128451A1 SG200307012A SG200307012A SG128451A1 SG 128451 A1 SG128451 A1 SG 128451A1 SG 200307012 A SG200307012 A SG 200307012A SG 200307012 A SG200307012 A SG 200307012A SG 128451 A1 SG128451 A1 SG 128451A1
- Authority
- SG
- Singapore
- Prior art keywords
- stop layer
- etch stop
- improved etch
- improved
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3148—Silicon Carbide layers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/335,589 US20040124420A1 (en) | 2002-12-31 | 2002-12-31 | Etch stop layer |
Publications (1)
Publication Number | Publication Date |
---|---|
SG128451A1 true SG128451A1 (en) | 2007-01-30 |
Family
ID=32655396
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200307012A SG128451A1 (en) | 2002-12-31 | 2003-11-28 | Improved etch stop layer |
Country Status (4)
Country | Link |
---|---|
US (2) | US20040124420A1 (zh) |
CN (1) | CN1245750C (zh) |
SG (1) | SG128451A1 (zh) |
TW (1) | TWI294647B (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3898133B2 (ja) * | 2003-01-14 | 2007-03-28 | Necエレクトロニクス株式会社 | SiCHN膜の成膜方法。 |
US7067437B2 (en) * | 2003-09-12 | 2006-06-27 | International Business Machines Corporation | Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same |
US7115974B2 (en) * | 2004-04-27 | 2006-10-03 | Taiwan Semiconductor Manfacturing Company, Ltd. | Silicon oxycarbide and silicon carbonitride based materials for MOS devices |
US7422776B2 (en) * | 2004-08-24 | 2008-09-09 | Applied Materials, Inc. | Low temperature process to produce low-K dielectrics with low stress by plasma-enhanced chemical vapor deposition (PECVD) |
US20060286306A1 (en) * | 2005-06-17 | 2006-12-21 | Asm Japan K.K. | Method of producing advanced low dielectric constant film by UV light emission |
KR100706822B1 (ko) * | 2005-10-17 | 2007-04-12 | 삼성전자주식회사 | 절연 물질 제거용 조성물, 이를 이용한 절연막의 제거 방법및 기판의 재생 방법 |
US7789965B2 (en) * | 2006-09-19 | 2010-09-07 | Asm Japan K.K. | Method of cleaning UV irradiation chamber |
US20090093135A1 (en) * | 2007-10-04 | 2009-04-09 | Asm Japan K.K. | Semiconductor manufacturing apparatus and method for curing material with uv light |
US20110204382A1 (en) * | 2008-05-08 | 2011-08-25 | Base Se | Layered structures comprising silicon carbide layers, a process for their manufacture and their use |
US20100059762A1 (en) * | 2008-09-08 | 2010-03-11 | Spansion Llc | Heat removal facilitated with diamond-like carbon layer in soi structures |
US20100252930A1 (en) * | 2009-04-01 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Improving Performance of Etch Stop Layer |
CN102044473B (zh) * | 2009-10-13 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
US8993435B2 (en) * | 2010-03-15 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-k Cu barriers in damascene interconnect structures |
US8969997B2 (en) * | 2012-11-14 | 2015-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structures and methods of forming the same |
US9370907B2 (en) | 2014-03-20 | 2016-06-21 | Seagate Technology Llc | Apparatuses and methods utilizing etch stop layers |
US20170278700A1 (en) * | 2014-09-26 | 2017-09-28 | John D. Brooks | Technique for oxidizing plasma post-treatment for reducing photolithography poisoning and associated structures |
US10685873B2 (en) * | 2016-06-29 | 2020-06-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch stop layer for semiconductor devices |
CN109153255A (zh) * | 2016-07-12 | 2019-01-04 | 惠普发展公司,有限责任合伙企业 | 包括薄膜钝化层的印刷头 |
CN111952168B (zh) * | 2020-08-18 | 2022-11-25 | 上海华力微电子有限公司 | 刻蚀工艺的切换方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6383943B1 (en) * | 2000-10-16 | 2002-05-07 | Taiwan Semiconductor Manufacturing Company | Process for improving copper fill integrity |
US6468894B1 (en) * | 2001-03-21 | 2002-10-22 | Advanced Micro Devices, Inc. | Metal interconnection structure with dummy vias |
US20030176058A1 (en) * | 2002-03-18 | 2003-09-18 | Applies Materials, Inc. | Method of forming a dual damascene structure using an amorphous silicon hard mask |
US20030181034A1 (en) * | 2002-03-19 | 2003-09-25 | Ping Jiang | Methods for forming vias and trenches with controlled SiC etch rate and selectivity |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100207444B1 (ko) * | 1995-03-14 | 1999-07-15 | 윤종용 | 반도체 장치의 고유전막/전극 및 그 제조방법 |
US6627532B1 (en) * | 1998-02-11 | 2003-09-30 | Applied Materials, Inc. | Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition |
US6974766B1 (en) | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
US6255217B1 (en) * | 1999-01-04 | 2001-07-03 | International Business Machines Corporation | Plasma treatment to enhance inorganic dielectric adhesion to copper |
US6492267B1 (en) * | 2000-02-11 | 2002-12-10 | Micron Technology, Inc. | Low temperature nitride used as Cu barrier layer |
JP3934343B2 (ja) * | 2000-07-12 | 2007-06-20 | キヤノンマーケティングジャパン株式会社 | 半導体装置及びその製造方法 |
US6764958B1 (en) * | 2000-07-28 | 2004-07-20 | Applied Materials Inc. | Method of depositing dielectric films |
US6548892B1 (en) * | 2000-08-31 | 2003-04-15 | Agere Systems Inc. | Low k dielectric insulator and method of forming semiconductor circuit structures |
US6583048B2 (en) * | 2001-01-17 | 2003-06-24 | Air Products And Chemicals, Inc. | Organosilicon precursors for interlayer dielectric films with low dielectric constants |
US6759327B2 (en) * | 2001-10-09 | 2004-07-06 | Applied Materials Inc. | Method of depositing low k barrier layers |
US20030087043A1 (en) * | 2001-11-08 | 2003-05-08 | International Business Machines Corporation | Low k dielectric film deposition process |
US6890850B2 (en) * | 2001-12-14 | 2005-05-10 | Applied Materials, Inc. | Method of depositing dielectric materials in damascene applications |
US7226853B2 (en) * | 2001-12-26 | 2007-06-05 | Applied Materials, Inc. | Method of forming a dual damascene structure utilizing a three layer hard mask structure |
US6541397B1 (en) * | 2002-03-29 | 2003-04-01 | Applied Materials, Inc. | Removable amorphous carbon CMP stop |
US6770570B2 (en) * | 2002-11-15 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer |
-
2002
- 2002-12-31 US US10/335,589 patent/US20040124420A1/en not_active Abandoned
-
2003
- 2003-06-05 TW TW092115180A patent/TWI294647B/zh not_active IP Right Cessation
- 2003-08-08 CN CNB031531903A patent/CN1245750C/zh not_active Expired - Lifetime
- 2003-11-28 SG SG200307012A patent/SG128451A1/en unknown
-
2006
- 2006-01-05 US US11/325,935 patent/US7375040B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6383943B1 (en) * | 2000-10-16 | 2002-05-07 | Taiwan Semiconductor Manufacturing Company | Process for improving copper fill integrity |
US6468894B1 (en) * | 2001-03-21 | 2002-10-22 | Advanced Micro Devices, Inc. | Metal interconnection structure with dummy vias |
US20030176058A1 (en) * | 2002-03-18 | 2003-09-18 | Applies Materials, Inc. | Method of forming a dual damascene structure using an amorphous silicon hard mask |
US20030181034A1 (en) * | 2002-03-19 | 2003-09-25 | Ping Jiang | Methods for forming vias and trenches with controlled SiC etch rate and selectivity |
Also Published As
Publication number | Publication date |
---|---|
US7375040B2 (en) | 2008-05-20 |
CN1245750C (zh) | 2006-03-15 |
US20040124420A1 (en) | 2004-07-01 |
CN1514477A (zh) | 2004-07-21 |
US20060110938A1 (en) | 2006-05-25 |
TW200411765A (en) | 2004-07-01 |
TWI294647B (en) | 2008-03-11 |
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