SG126076A1 - Laminated layer structure and method for forming the same - Google Patents

Laminated layer structure and method for forming the same

Info

Publication number
SG126076A1
SG126076A1 SG200601698A SG200601698A SG126076A1 SG 126076 A1 SG126076 A1 SG 126076A1 SG 200601698 A SG200601698 A SG 200601698A SG 200601698 A SG200601698 A SG 200601698A SG 126076 A1 SG126076 A1 SG 126076A1
Authority
SG
Singapore
Prior art keywords
forming
same
layer structure
laminated layer
laminated
Prior art date
Application number
SG200601698A
Other languages
English (en)
Inventor
Christophe Figuet
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG126076A1 publication Critical patent/SG126076A1/en

Links

Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V33/00—Structural combinations of lighting devices with other articles, not otherwise provided for
    • F21V33/0004—Personal or domestic articles
    • F21V33/0012—Furniture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21K—NON-ELECTRIC LIGHT SOURCES USING LUMINESCENCE; LIGHT SOURCES USING ELECTROCHEMILUMINESCENCE; LIGHT SOURCES USING CHARGES OF COMBUSTIBLE MATERIAL; LIGHT SOURCES USING SEMICONDUCTOR DEVICES AS LIGHT-GENERATING ELEMENTS; LIGHT SOURCES NOT OTHERWISE PROVIDED FOR
    • F21K9/00—Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers
    • F21K9/60—Optical arrangements integrated in the light source, e.g. for improving the colour rendering index or the light extraction
    • F21K9/64—Optical arrangements integrated in the light source, e.g. for improving the colour rendering index or the light extraction using wavelength conversion means distinct or spaced from the light-generating element, e.g. a remote phosphor layer
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V23/00—Arrangement of electric circuit elements in or on lighting devices
    • F21V23/003—Arrangement of electric circuit elements in or on lighting devices the elements being electronics drivers or controllers for operating the light source, e.g. for a LED array
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V23/00—Arrangement of electric circuit elements in or on lighting devices
    • F21V23/04—Arrangement of electric circuit elements in or on lighting devices the elements being switches
    • F21V23/0442—Arrangement of electric circuit elements in or on lighting devices the elements being switches activated by means of a sensor, e.g. motion or photodetectors
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V3/00—Globes; Bowls; Cover glasses
    • F21V3/04—Globes; Bowls; Cover glasses characterised by materials, surface treatments or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2115/00—Light-generating elements of semiconductor light sources
    • F21Y2115/10—Light-emitting diodes [LED]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Public Health (AREA)
  • Optics & Photonics (AREA)
  • Recrystallisation Techniques (AREA)
  • Chemical Vapour Deposition (AREA)
SG200601698A 2005-03-21 2006-03-15 Laminated layer structure and method for forming the same SG126076A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP05290622A EP1705697A1 (en) 2005-03-21 2005-03-21 Composition graded layer structure and method for forming the same

Publications (1)

Publication Number Publication Date
SG126076A1 true SG126076A1 (en) 2006-10-30

Family

ID=36710458

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200601698A SG126076A1 (en) 2005-03-21 2006-03-15 Laminated layer structure and method for forming the same

Country Status (7)

Country Link
US (1) US7387953B2 (zh)
EP (1) EP1705697A1 (zh)
JP (1) JP2006319310A (zh)
KR (1) KR100788422B1 (zh)
CN (1) CN1838429A (zh)
SG (1) SG126076A1 (zh)
TW (1) TWI288433B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1763069B1 (en) * 2005-09-07 2016-04-13 Soitec Method for forming a semiconductor heterostructure
US7785995B2 (en) * 2006-05-09 2010-08-31 Asm America, Inc. Semiconductor buffer structures
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
US9171715B2 (en) 2012-09-05 2015-10-27 Asm Ip Holding B.V. Atomic layer deposition of GeO2
FR2995447B1 (fr) * 2012-09-07 2014-09-05 Soitec Silicon On Insulator Procede de separation d'au moins deux substrats selon une interface choisie
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
KR20170066914A (ko) * 2015-12-07 2017-06-15 삼성전자주식회사 반도체 장치 제조 방법
WO2022036591A1 (zh) * 2020-08-19 2022-02-24 西门子股份公司 增材制造中的打印工艺制定方法及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5442205A (en) 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
JP4269541B2 (ja) 2000-08-01 2009-05-27 株式会社Ｓｕｍｃｏ 半導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
US6649492B2 (en) * 2002-02-11 2003-11-18 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
GB0212616D0 (en) * 2002-05-31 2002-07-10 Univ Warwick Formation of lattice-tuning semiconductor substrates
EP2267762A3 (en) * 2002-08-23 2012-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US7129488B2 (en) * 2003-12-23 2006-10-31 Sharp Laboratories Of America, Inc. Surface-normal optical path structure for infrared photodetection

Also Published As

Publication number Publication date
US20060211230A1 (en) 2006-09-21
CN1838429A (zh) 2006-09-27
KR20060101799A (ko) 2006-09-26
EP1705697A1 (en) 2006-09-27
TWI288433B (en) 2007-10-11
KR100788422B1 (ko) 2007-12-24
JP2006319310A (ja) 2006-11-24
TW200634911A (en) 2006-10-01
US7387953B2 (en) 2008-06-17

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