SG118299A1 - Integrated circuit structure and method of fabrication - Google Patents

Integrated circuit structure and method of fabrication

Info

Publication number
SG118299A1
SG118299A1 SG200407626A SG200407626A SG118299A1 SG 118299 A1 SG118299 A1 SG 118299A1 SG 200407626 A SG200407626 A SG 200407626A SG 200407626 A SG200407626 A SG 200407626A SG 118299 A1 SG118299 A1 SG 118299A1
Authority
SG
Singapore
Prior art keywords
fabrication
integrated circuit
circuit structure
integrated
circuit
Prior art date
Application number
SG200407626A
Other languages
English (en)
Inventor
Lin Chuan-Yi
Wu Shien-Yang
Yeo Yee-Chia
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of SG118299A1 publication Critical patent/SG118299A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
SG200407626A 2004-06-25 2004-12-22 Integrated circuit structure and method of fabrication SG118299A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/877,441 US7271431B2 (en) 2004-06-25 2004-06-25 Integrated circuit structure and method of fabrication

Publications (1)

Publication Number Publication Date
SG118299A1 true SG118299A1 (en) 2006-01-27

Family

ID=35506439

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200407626A SG118299A1 (en) 2004-06-25 2004-12-22 Integrated circuit structure and method of fabrication

Country Status (4)

Country Link
US (1) US7271431B2 (zh)
CN (1) CN100449757C (zh)
SG (1) SG118299A1 (zh)
TW (1) TWI240375B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060194400A1 (en) * 2005-01-21 2006-08-31 Cooper James A Method for fabricating a semiconductor device
KR100928504B1 (ko) * 2007-10-19 2009-11-26 주식회사 동부하이텍 반도체 소자 및 반도체 소자의 제조방법
US8143137B2 (en) * 2010-02-17 2012-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device by thinning hardmask layers on frontside and backside of substrate
KR101137931B1 (ko) * 2010-03-03 2012-05-09 에스케이하이닉스 주식회사 반도체 장치의 핀 캐패시터 및 그 제조방법
US9048261B2 (en) * 2011-08-04 2015-06-02 International Business Machines Corporation Fabrication of field-effect transistors with atomic layer doping
CN102347268B (zh) * 2011-10-28 2015-07-22 上海华虹宏力半导体制造有限公司 半导体器件的制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100510232B1 (ko) * 1996-02-21 2005-10-27 텍사스 인스트루먼츠 인코포레이티드 반도체장치에서리필층두께의불균일성을줄이는방법
JPH1027799A (ja) * 1996-04-22 1998-01-27 Toshiba Corp 半導体装置及びその製造方法
JP3466874B2 (ja) * 1997-06-11 2003-11-17 株式会社東芝 半導体装置及びその製造方法
JPH11154675A (ja) * 1997-11-20 1999-06-08 Toshiba Corp 半導体装置及びその製造方法
US6146978A (en) * 1998-05-06 2000-11-14 Advanced Micro Devices, Inc. Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance
US6303484B1 (en) * 2000-01-12 2001-10-16 United Microelectronics Corp. Method of manufacturing dummy pattern
US6355524B1 (en) * 2000-08-15 2002-03-12 Mosel Vitelic, Inc. Nonvolatile memory structures and fabrication methods
US6559055B2 (en) * 2000-08-15 2003-05-06 Mosel Vitelic, Inc. Dummy structures that protect circuit elements during polishing
JP2002134632A (ja) * 2000-10-20 2002-05-10 Hitachi Ltd 半導体集積回路装置の製造方法
US6406975B1 (en) * 2000-11-27 2002-06-18 Chartered Semiconductor Manufacturing Inc. Method for fabricating an air gap shallow trench isolation (STI) structure
US6506673B2 (en) * 2001-06-11 2003-01-14 Agere Systems Guardian Corp. Method of forming a reverse gate structure with a spin on glass process
US20030020086A1 (en) * 2001-07-25 2003-01-30 Motorola, Inc. Tuned delay components for an integrated circuit
JP2004072063A (ja) * 2002-06-10 2004-03-04 Nec Electronics Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
US20050287779A1 (en) 2005-12-29
TWI240375B (en) 2005-09-21
US7271431B2 (en) 2007-09-18
TW200601496A (en) 2006-01-01
CN100449757C (zh) 2009-01-07
CN1728383A (zh) 2006-02-01

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