SG11201909899SA - Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays - Google Patents

Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays

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Publication number
SG11201909899SA
SG11201909899SA SG11201909899SA SG11201909899SA SG 11201909899S A SG11201909899S A SG 11201909899SA SG 11201909899S A SG11201909899S A SG 11201909899SA SG 11201909899S A SG11201909899S A SG 11201909899SA
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Singapore
Prior art keywords
charge
elevationally
memory cells
holl
international
Prior art date
Application number
Inventor
Gurtej Sandhu
Richard Hill
John Smythe
Original Assignee
Micron Technology Inc
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Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201909899SA publication Critical patent/SG11201909899SA/en

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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment

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Abstract

FIG. 1 49 49 5 O O 00 O O (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 01 November 2018 (01.11.2018) WIPO I PCT omitia °nolo Hillis n ono oimIE (10) International Publication Number WO 2018/200133 Al (51) International Patent Classification: HOlL 27/11556 (2017.01) HOlL 27/11582 (2017.01) HOlL 27/11524 (2017.01) HOlL 27/1157 (2017.01) HOlL 27/11529 (2017.01) HOlL 27/11573 (2017.01) (21) International Application Number: PCT/US2018/025716 (22) International Filing Date: 02 April 2018 (02.04.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/581,762 28 April 2017 (28.04.2017) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way, Boise, ID 83716 (US). (72) Inventors: SANDHU, Gurtej, S.; 2964 East Parkriver Drive, Boise, ID 83706 (US). HILL, Richard, J.; 636 N. Morningside Way, Boise, ID 83712 (US). SMYTHE, John, A.; 4546 S. Riva Ridge Way, Boise, ID 83709 (US). (74) Agent: MATKIN, Mark, S. et al.; Wells St. John P.S., 601 W. Main Avenue, Suite 600, Spokane, WA 99201 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (54) Title: ARRAYS OF ELEVATIONALLY-EXTENDING STRINGS OF MEMORY CELLS AND METHODS OF FORMING MEMORY ARRAYS (57) : An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control-gate regions. Charge-storage material of individ- ual memory cells extend elevationally along individual of the control-gate regions of the wordline levels and do not extend elevation- ally along the insulative levels. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions of the wordline levels laterally through which charge migration between the individual control-gate regions and the charge-storage material is blocked. Channel material extends elevationally along the stack and is laterally spaced from the charge- storage material by insulative charge-passage material. All of the charge- storage material of individual of the elevationally-extending strings of memory cells is laterally outward of all of the insulative charge-passage material of the individual elevationally-extending strings of memory cells. Other embodiments, including method embodiments, are disclosed. [Continued on next page] WO 2018/200133 Al MIDEDIMOMOIDEIRDERIHIMINIMIIIIMOVOIMIE (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))
SG11201909899S 2017-04-28 2018-04-02 Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays SG11201909899SA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/581,762 US9985049B1 (en) 2017-04-28 2017-04-28 Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays
PCT/US2018/025716 WO2018200133A1 (en) 2017-04-28 2018-04-02 Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays

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US (2) US9985049B1 (en)
EP (1) EP3616240A4 (en)
JP (1) JP6890189B2 (en)
KR (1) KR102291999B1 (en)
CN (1) CN110574161A (en)
SG (1) SG11201909899SA (en)
TW (1) TWI671859B (en)
WO (1) WO2018200133A1 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10431591B2 (en) * 2017-02-01 2019-10-01 Micron Technology, Inc. NAND memory arrays
US10700087B2 (en) * 2017-10-12 2020-06-30 Applied Materials, Inc. Multi-layer stacks for 3D NAND extendibility
US10516025B1 (en) * 2018-06-15 2019-12-24 Sandisk Technologies Llc Three-dimensional NAND memory containing dual protrusion charge trapping regions and methods of manufacturing the same
US10593695B1 (en) * 2018-10-17 2020-03-17 Micron Technology, Inc. Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies
CN110914985B (en) * 2019-03-29 2021-04-27 长江存储科技有限责任公司 Three-dimensional memory device and method of fabricating the same
US11037944B2 (en) 2019-07-10 2021-06-15 Micron Technology, Inc. Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias
US10985179B2 (en) * 2019-08-05 2021-04-20 Micron Technology, Inc. Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias
US11024644B2 (en) * 2019-08-22 2021-06-01 Micron Technology, Inc. Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies
US11114534B2 (en) * 2019-12-27 2021-09-07 Sandisk Technologies Llc Three-dimensional nor array including vertical word lines and discrete channels and methods of making the same
WO2021163831A1 (en) * 2020-02-17 2021-08-26 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and fabrication methods thereof
KR20210106293A (en) * 2020-02-20 2021-08-30 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of semiconductor device
KR20210106295A (en) 2020-02-20 2021-08-30 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of semiconductor device
KR20210106294A (en) 2020-02-20 2021-08-30 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of semiconductor device
US11244953B2 (en) 2020-02-26 2022-02-08 Sandisk Technologies Llc Three-dimensional memory device including molybdenum word lines and metal oxide spacers and method of making the same
US11569260B2 (en) * 2020-02-26 2023-01-31 Sandisk Technologies Llc Three-dimensional memory device including discrete memory elements and method of making the same
US11538819B2 (en) 2020-07-16 2022-12-27 Micron Technology, Inc. Integrated circuitry, a method used in forming integrated circuitry, and a method used in forming a memory array comprising strings of memory cells
WO2022080842A1 (en) * 2020-10-13 2022-04-21 한양대학교 산학협력단 Three-dimensional flash memory, method for manufacturing same, and method for operating same
KR102504650B1 (en) * 2020-10-21 2023-02-28 한양대학교 산학협력단 Three dimensional flash memory for improving integration and manufactureing method thereof
JP2024047208A (en) * 2022-09-26 2024-04-05 株式会社Kokusai Electric SUBSTRATE PROCESSING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD,

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009158775A (en) * 2007-12-27 2009-07-16 Toshiba Corp Nonvolatile semiconductor memory device and method of manufacturing the same
EP2225774A4 (en) * 2007-12-27 2013-04-24 Toshiba Kk Semiconductor memory device and method for manufacturing same
KR101585616B1 (en) * 2009-12-16 2016-01-15 삼성전자주식회사 Semiconductor device and method for fabricating the same
CN102959693B (en) * 2010-06-30 2015-08-19 桑迪士克科技股份有限公司 Super-high density is vertical with non-memory device and manufacture method thereof
US9227456B2 (en) * 2010-12-14 2016-01-05 Sandisk 3D Llc Memories with cylindrical read/write stacks
US8946808B2 (en) * 2012-02-09 2015-02-03 SK Hynix Inc. Semiconductor device and method of manufacturing the same
US8946807B2 (en) 2013-01-24 2015-02-03 Micron Technology, Inc. 3D memory
US9064547B2 (en) * 2013-03-05 2015-06-23 Sandisk 3D Llc 3D non-volatile memory having low-current cells and methods
KR102059525B1 (en) * 2013-03-19 2019-12-27 삼성전자주식회사 Vertical Cell Type Semiconductor Device Having a Protective Pattern
US9478643B2 (en) * 2013-12-24 2016-10-25 Intel Corporation Memory structure with self-aligned floating and control gates and associated methods
JP2017010951A (en) * 2014-01-10 2017-01-12 株式会社東芝 Semiconductor memory and its manufacturing method
WO2015105049A2 (en) * 2014-01-10 2015-07-16 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same
US9583539B2 (en) 2014-08-19 2017-02-28 Sandisk Technologies Llc Word line connection for memory device and method of making thereof
US9257443B1 (en) * 2014-09-09 2016-02-09 Kabushiki Kaisha Toshiba Memory device and method for manufacturing the same
US9793124B2 (en) 2014-10-07 2017-10-17 Micron Technology, Inc. Semiconductor structures
US9484357B2 (en) * 2014-12-16 2016-11-01 Sandisk Technologies Llc Selective blocking dielectric formation in a three-dimensional memory structure
US9515079B2 (en) * 2014-12-16 2016-12-06 Sandisk Technologies Llc Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack
US9530781B2 (en) * 2014-12-22 2016-12-27 Sandisk Technologies Llc Three dimensional NAND memory having improved connection between source line and in-hole channel material as well as reduced damage to in-hole layers
US9595342B2 (en) * 2015-01-20 2017-03-14 Sandisk Technologies Llc Method and apparatus for refresh programming of memory cells based on amount of threshold voltage downshift
US9627397B2 (en) * 2015-07-20 2017-04-18 Macronix International Co., Ltd. Memory device and method for fabricating the same
JP6434877B2 (en) * 2015-08-26 2018-12-05 東芝メモリ株式会社 Semiconductor device

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