SG11201908769TA - Vertical gallium nitride schottky diode - Google Patents

Vertical gallium nitride schottky diode

Info

Publication number
SG11201908769TA
SG11201908769TA SG11201908769TA SG11201908769TA SG 11201908769T A SG11201908769T A SG 11201908769TA SG 11201908769T A SG11201908769T A SG 11201908769TA SG 11201908769T A SG11201908769T A SG 11201908769TA
Authority
SG
Singapore
Prior art keywords
gallium nitride
epitaxial
nitride layer
international
type gallium
Prior art date
Application number
Inventor
Vladimir Odnoblyudov
Ozgur Aktas
Original Assignee
Qromis Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qromis Inc filed Critical Qromis Inc
Publication of SG11201908769TA publication Critical patent/SG11201908769TA/en

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    • HELECTRICITY
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204Diodes
    • H01L29/66212Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • HELECTRICITY
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02439Materials
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

WO 18/ 18337 4 Al (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 04 October 2018 (04.10.2018) W I PO I PCT IiiimmoimiolollmonolomoniinociloimimiovoimIE (10) International Publication Number WO 2018/183374 Al (51) International Patent Classification: HOlL 29/872 (2006.01) HOlL 29/47 (2006.01) HO1L 29/45 (2006.01) (21) International Application Number: PCT/US2018/024629 (22) International Filing Date: 27 March 2018 (27.03.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/478,483 29 March 2017 (29.03.2017) US 15/936,305 26 March 2018 (26.03.2018) US (71) Applicant: QROMIS, INC. [US/US]; 2306 Walsh Av- enue, Santa Clara, California 95051 (US). (72) Inventors: ODNOBLYUDOV, Vladimir; c/o Qromis, Inc., 2306 Walsh Avenue, Santa Clara, California 95032 (US). AKTAS, Ozgur; c/o Qromis, Inc., 2306 Walsh Av- enue, Santa Clara, California 95051 (US). (74) Agent: LIU, Rong et al.; KILPATRICK TOWNSEND & STOCKTON LLP, Mailstop: IP Docketing-22, 1100 Peachtree Street, Suite 2800, Atlanta, Georgia 30309 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 2 I (3)) (54) Title: VERTICAL GALLIUM NITRIDE SCHOTTKY DIODE (57) : A vertical Schottky diode includes an ohmic contact, a first epitaxial N-type gallium nitride layer physically contacting the ohmic contact and having a first doping concentration, and a sec- ond epitaxial N-type gallium nitride layer physically contacting the 520 518 first epitaxial N-type gallium nitride layer and having a second dop- ing concentration that is lower than the first doping concentration. 522 The vertical Schottky diode further includes a first edge termination region and a second edge termination region coupled to the second 510-1 516 epitaxial N-type gallium nitride layer and separated from each other 512 by a portion of the second epitaxial N-type gallium nitride layer, and a Schottky contact coupled to the portion of the second epitaxial N- type gallium nitride layer, and to the first edge termination region and the second edge termination region. Fla 5 500
SG11201908769T 2017-03-29 2018-03-27 Vertical gallium nitride schottky diode SG11201908769TA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762478483P 2017-03-29 2017-03-29
US15/936,305 US10411108B2 (en) 2017-03-29 2018-03-26 Vertical gallium nitride Schottky diode
PCT/US2018/024629 WO2018183374A1 (en) 2017-03-29 2018-03-27 Vertical gallium nitride schottky diode

Publications (1)

Publication Number Publication Date
SG11201908769TA true SG11201908769TA (en) 2019-10-30

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SG11201908769T SG11201908769TA (en) 2017-03-29 2018-03-27 Vertical gallium nitride schottky diode

Country Status (8)

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US (2) US10411108B2 (en)
EP (1) EP3602635A4 (en)
JP (1) JP7190245B2 (en)
KR (1) KR20190133232A (en)
CN (1) CN110582852B (en)
SG (1) SG11201908769TA (en)
TW (1) TWI803485B (en)
WO (1) WO2018183374A1 (en)

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KR102275146B1 (en) * 2019-05-20 2021-07-08 파워큐브세미 (주) Schottky diode and method for fabricating the same
CN110676308B (en) * 2019-10-12 2022-12-20 中国电子科技集团公司第十三研究所 Preparation method of Schottky diode
CN111146294B (en) * 2019-12-05 2023-11-07 中国电子科技集团公司第十三研究所 Schottky diode and preparation method thereof
CN114864760A (en) * 2021-02-03 2022-08-05 厦门三安光电有限公司 Micro light-emitting diode and display panel
CN114141884A (en) * 2021-12-14 2022-03-04 上海集成电路制造创新中心有限公司 Reconfigurable schottky diode
WO2024137722A2 (en) * 2022-12-19 2024-06-27 Peiching Ling Semiconductor structures and memory devices and methods for manufacturing the same

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JP2020512698A (en) 2020-04-23
KR20190133232A (en) 2019-12-02
US20190334015A1 (en) 2019-10-31
TWI803485B (en) 2023-06-01
EP3602635A4 (en) 2020-12-23
WO2018183374A1 (en) 2018-10-04
JP7190245B2 (en) 2022-12-15
CN110582852A (en) 2019-12-17
US10411108B2 (en) 2019-09-10
EP3602635A1 (en) 2020-02-05
CN110582852B (en) 2024-05-17
TW201838194A (en) 2018-10-16
US20180286964A1 (en) 2018-10-04

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