200921776 九、發明說明： 【發明所屬之技術領域】 本發明係有關-種半導體封裝技術，特別是—種晶圓切 割方法、晶粒結構及其多晶粒封裂方法。 【先前技術】 1寻既的晶；ΐ級封装 g日日耻王日日_上切割下來再做封 之後’將晶粒設置於基板上。晶粒與基板係利用接線製 以複數條導線電性連接再堆疊晶粒於其上。，以 材料覆蓋晶粒、基板與導線。然 ' , n Bg 、s ά…、而於接線過程中可能會發 ^多問4。例如’導線之線弧容易 ，，導致電性短路問題並降低產品=緣= 於打線接合製㈣《造成晶粒„及產品撞料問^曰片 【發明内容】 割方二了日解本發明目狀—係提供—種晶圓切 之接㈣：： 粒封裝方法，可捨去晶粒封裝時 、’程’故可避免接線製程可能產生之問題。 其多曰本目Γ ί—係提供—種晶圓切割方法、晶粒結構及 各以=之:::灌注成型技術，將導電材料-入 達到晶之預留空間與基板上焊接點相互連接，以 发夕，發明目的之—係提供—種晶圓切割方法、晶粒 ，、夕曰曰教封裝方法，係利用絕緣材料於晶圓接割時於 200921776 成預留空間供其後則灌注成型技術，將導電材料注 入各阳粒及其焊接墊之預留空間與基板上焊接點相互連接。 盆夕曰本發明目的之-係提供—種晶圓切割方法、晶粒結構及 封裝方法，係可縮減因接線―限的空間，充 =揮基板之板材利用率，可有效縮短製程⑽) 並降低成本。 ^了達到上述目的，本發明—實施例之晶圓切割方法， 二a二列步驟提供—晶圓;形成複數個切割凹槽於晶圓之主動 是數個晶粒區域；形成一圖案化第一絕緣層於晶圓之主動面 切割凹槽；形成-圖案化第二絕緣層於第—圖案化絕緣層上； 圓背面至暴露出切割凹槽内之圖案化第—絕緣層；以及沿著切 進订切割以獲得複數個晶粒。其令，圖案化第一絕緣層具有複 j口暴露出晶圓主動面上複數個谭接墊；圖案化第二絕緣層係具 2數個溝道暴露出圖案化第—絕緣層之開口；圖案化第一絕緣層係 匕覆晶粒之側壁；以及開σ與溝道係組成導引至焊接墊之一通道。 本土明另-實施例之晶粒結構，係包括：一晶粒；一圖案200921776 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor packaging techniques, particularly wafer cutting methods, grain structures, and multi-die sealing methods. [Prior Art] 1 Finder both crystals; ΐ-level package g DAY DAY DAY _ 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上 上The die and the substrate are electrically connected by a plurality of wires and then stacked on the die. Cover the die, substrate and wire with material. However, ', n Bg, s ά..., and may ask 4 in the wiring process. For example, 'the wire arc of the wire is easy, which leads to the problem of electrical short circuit and lowers the product = edge = the wire bonding system (4) "causes the grain „ and the product collision material ^ 曰 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 Shape--providing a kind of wafer cutting connection (4):: The grain encapsulation method can eliminate the problem that the wiring process may be caused when the chip is packaged, and the process can be avoided. Wafer cutting method, grain structure and each of the following:::infusion molding technology, the conductive material-into the crystal reserved space and the solder joint on the substrate are connected to each other, for the purpose of the invention - provide - The wafer cutting method, the die, and the Xi'an encapsulation method are made by using the insulating material to form a reserved space for the wafer cutting in 200921776, and then injecting the conductive material into the positive particles and The reserved space of the solder pad is interconnected with the solder joint on the substrate. The purpose of the present invention is to provide a wafer cutting method, a grain structure and a packaging method, which can reduce the space due to wiring, and charge = Slab plate The utilization rate can effectively shorten the process (10)) and reduce the cost. ^ To achieve the above object, the wafer cutting method of the present invention - the embodiment, the second and second steps provide the wafer; and form a plurality of cutting grooves on the wafer The active is a plurality of die regions; forming a patterned first insulating layer to cut the groove on the active surface of the wafer; forming a patterned second insulating layer on the first patterned insulating layer; and rounding the back surface to expose the concave recess a patterned first-insulating layer in the trench; and a cut-to-cut cut to obtain a plurality of crystal grains, wherein the patterned first insulating layer has a plurality of tan pads exposed on the active surface of the wafer; The patterned second insulating layer is provided with a plurality of channels exposing the openings of the patterned first insulating layer; the patterned first insulating layer is covering the sidewalls of the crystal grains; and the opening σ and the channel system are guided to the soldering One of the channels of the pad. The local grain structure of the embodiment includes: a die; a pattern
化苐=絕緣層係包覆晶粒之側壁與主動面；—圖案化第二絕緣層係設 第-圖案化絕緣層上H _化第_絕緣層具有複數個開口 暴你出晶粒主動面上複數個焊接塾；圖案化第二絕緣層係具有複數個 溝運暴露出圖案化第-絕緣層之開口；以及開口與溝道係組成導引至 焊接墊之一通道。 本發月X戶、施例之多晶粒封裝方法係包括下列步 驟：提供-基板；提供至少兩晶粒相互堆疊設置於基板上；提供一 板具包覆日日粒與。卩域板，係用以注人—導電材料形成—導電結構； 以及提供-封裝材料，係用以包覆基板、晶粒與導電結構。其中，一 黏著層係π置&每-晶粒之底部；__圖案化第—絕緣層係包覆晶粒之 側壁與主動面，®案化第—絕緣層具有複數觸口暴露出晶粒主動面 6 200921776 上複數個焊接塾；-圖案化第二絕緣層係設置於第一圖案化絕緣層 上；®案化第二絕緣層係具有複數觸道暴露出随化第一絕緣層之 開口；以及開口與溝道係組成糾至焊接墊之—通道^，導電結構 . 得'包含一内接導電部與一外接導電部，内接導電部係與焊接塾連接並 填滿通道’騎接導電部係連接内接導電部並沿著晶粒之側壁呈一柱 狀與基板的複數個焊接點連接。 【實施方式】 明眚=2 1B'圖le、圖1D、圖1_ 1F所示為根據本發 月-實施L謂方法之流㈣_。於本實 ;刀割:=下列步驟。首先，請參照圖1A，提供—晶； 凹二者二圖把所示，於晶圓10主動面形成複數個切割 =二定特定深度並不會貫 機村〇複數個晶粒區域。切割凹槽12可利用蝕刻、 機械裁切或雷射切割的方式所形成。 上述說明’清參照圖1C，形成一圖案化第—絕緣声2〇 =。之主動面並填滿切割凹槽12。其中，圖案化 二 具树數個開口 21暴露出晶圓1〇主動面上 、= 不）。接著，如圖1D所示，形屮π牧至I圖上未 案化絕緣層20上。此圖_ ^—麵^賴22於第一圖 露出圖案化第-節t _#道23暴 層20與圖案化第二絕緣層22係利：了不-圖案化第-絕緣 形成，且圖案化第一絕緣層2邀土 re_C〇atlng)方式所 a— - s U與圖案化第二絕緣層22係A助# 扣' 二氧切（Si〇2)或氮切（ 酸亞 如圖1E所示，對晶圓1〇之背 露出：。接著， 磨。之後’沿綱_12細__數㈣=械式研 7 200921776 圖IF所示為根據本發明一實施例晶粒結構之示意圖。於本實 施例中，利用上述方法所製成之晶粒結構，其特徵在於一圖案化第 -絕緣層2G包覆晶粒14之側壁與主動面，且酸化第_絕緣層2〇 具有複數綱口 21暴露出晶粒14主動面上複數個焊接塾15，請同時 參照圖2A與圖2B。另外，一圖案化第二絕緣層22係設置於第一圖 案化絕緣層2G上，且目案化第二絕緣層22係具魏數赠道23暴 露出圖案化第-絕緣層2G之開口 2卜開口 21與溝道23係組成導引 至焊接墊15之一通道。其中，圖案化第一絕緣層2〇細案化第二絕 緣層22之材質係為聚醯亞胺、二氧化矽或氮化矽等絕緣材質。 請參照圖2A與圖2B，於一實施例中，晶粒14設置於 基板100上時，係利用一黏著層（圖上未標）固定於基板1〇〇 上。圖案化第一絕緣層20之開口 21與圖案化第二絕緣層22之溝道 23係組成導引至4接墊15之一通道。利用灌注成型技術，將導 電材料注入晶粒主動面及其焊接墊之通道（預留空間）與基 板100上焊接點102相互連接，就可達到晶粒14與基板1〇〇 之導通。 、 圖3A、圖3B、圖3C與圖3D所示為根據本發明一實施 例多晶粒封裝方法之流程剖面示意圖。首先，如圖3 A所示， 提供一基板100並相互堆疊複數個晶粒14於基板100上。一黏著層 邓係設置於每一晶粒Μ之底部…圖案化第一絕緣層2〇係包覆晶粒 4之側壁與主動面。此圖案化第一絕緣層2〇具有複數個開口（圖上 未標）暴露出晶粒14主動面上複數個焊接塾（圖上未標_圖案化 第二絕緣層22係設置於第一圖案化絕緣層2〇上。此圖案化第二絕緣 層22係具有複數個溝道（圖上未標）暴露出圖案化第一絕緣層2〇之 開口。圖案化第一絕緣層20之開口與圖案化第二絕緣層22盖 叙成導引至晶粒14焊接塾（圖上未標）之—通道。其中，圖案化第 一絕緣層20與圖案化第二絕緣層22之材質係為聚醯亞胺、二氧 化矽或氮化矽等絕緣材質。 200921776 接續上述說明，如圖3B與圖3C所示，提供_模具如 粒14與部份基板1〇〇。由模具40之灌注孔注入_導電 L， 電結構5〇。導電材料係為一液態金屬或一液態導電材料。此導 50係包含一内接導電部52與一外接導電部54且此導電，結辑 用灌注成型技術所製成。其中，接導電部52係與晶粒&之，利 (圖上未標）連接並填滿通道，而外接導電部54係連接 ' =勢 52並沿著晶粒14之側壁呈一柱狀與基板1〇〇的複數個焊接點$部 未標）連接。之後，如圖3D所示，提供一封裝材料6〇用以= 100、晶粒14與導電結構5〇。 復基板 圖4A、圖4B與圖4C所示為根據本發明 =裝方法不同剖面方向之流程示意圖。於本實施例次日曰曰 豐於基板_後’利用灌注成型技術製成導電結構二 構％係與^ 14之焊接墊（圖上未標）連魅填滿通道， Μ =粒M之侧壁呈""'柱狀與基板1GG的複數個焊接點（圖上未 ii: 2後’提供—封裝㈣6G用以包覆基板⑽、晶粒14與 合上述’本發明係利用灌注成型技術，將導電材料注 入晶粒及其焊接塾之預留空間與基板上焊接點相互連接， j到晶粒串接導通。此預留空間係利用絕緣材料於晶圓切 β、於阳粒主動面形成。本發明可捨去晶粒封裝時之接線製 ^呈故可避免接線製程可能產生之問題。本發明亦可縮減因 t製程所碰的空間’充分發揮基板之板材利用率，可有 效縮短製程時間並降低成本 以上所述之實施例僅係為說明本發明之技術思想及特 ·、、、目的在使熟習此項技藝之人士能夠瞭解本發明之内容 並據以實施’當不能以之限定本發明之專利範圍，即大凡依 200921776 本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本 發明之專利範圍内。 【圖式簡單說明】 圖1A、圖1B、圖1C、圖1D、圖1E與圖1F所示為根據本發明一 實施例之示意圖。 圖2A與圖2B所示為根據本發明一實施例之示意圖。 圖3A、圖3B、圖3C與圖3D所示為根據本發明一實施例之示意圖。 圖4A、圖4B與圖4C所示為根據本發明一實施例之示意圖。 【主要元件符號說明】 100 基板 102 焊接點 10 晶圓 14 晶粒 15 焊接墊 20 圖案化第一絕緣層 21 開口 22 圖案化第二絕緣層 23 溝道 30 黏著層 40 模具 10 200921776 50 導電結構 . 52 内接導電部 . 54 外接導電部 60 封裝材料 11苐 苐 = the insulating layer is coated with the sidewalls of the die and the active surface; - the patterned second insulating layer is provided with the first - patterned insulating layer on the H - _ the first insulating layer has a plurality of openings, and the active surface of the die The plurality of soldering rafts are patterned; the patterned second insulating layer has a plurality of openings for exposing the patterned first insulating layer; and the openings and the channel structures are guided to one of the channels of the solder pads. The multi-die encapsulation method of the present invention includes the following steps: providing a substrate; providing at least two crystal grains stacked on each other on the substrate; and providing a plate with a coating of the solar particles. The 卩 domain plate is used for injecting a conductive material to form a conductive structure; and providing a packaging material for covering the substrate, the die and the conductive structure. Wherein, an adhesive layer is π-set and the bottom of each of the grains; __ patterned first-insulating layer covers the sidewalls of the die and the active surface, and the patterned first-insulating layer has a plurality of contacts exposing the crystal Granular active surface 6 200921776 has a plurality of soldering rafts; - patterned second insulating layer is disposed on the first patterned insulating layer; and the second insulating layer has a plurality of contacts exposed to the first insulating layer The opening and the channel are formed to be etched into the soldering pad - the channel ^, the conductive structure. The 'contains an inscribed conductive portion and an external conductive portion, and the inner conductive portion is connected to the solder joint and fills the channel' The conductive portion is connected to the internal conductive portion and connected to the plurality of solder joints of the substrate in a column shape along the sidewall of the die. [Embodiment] Alum = 2 1B' diagram le, Fig. 1D, and Fig. 1_1F show a stream (4)_ according to the present embodiment. In this real; knife cut: = the following steps. First, please refer to FIG. 1A, which provides a crystal; the concave two shows that forming a plurality of cuts on the active surface of the wafer 10 = two specific depths does not pass through a plurality of grain regions. The cutting groove 12 can be formed by etching, mechanical cutting or laser cutting. The above description has been made with reference to Fig. 1C to form a patterned first insulating sound 2 〇 =. The active surface fills the cutting groove 12. Wherein, the patterning of the plurality of openings 21 of the tree exposes the wafer 1 active surface, = no). Next, as shown in Fig. 1D, the shape 屮 牧 is pasted onto the uninsulated insulating layer 20 on the I picture. This figure _ ^ - face 22 in the first figure reveals the patterned section - section t _ # 23 23 layer 23 and the patterned second insulating layer 22 is profit: not - patterned first - insulation formation, and pattern The first insulating layer 2 invites the soil re_C〇atlng) mode a--s U and the patterned second insulating layer 22 is A-assisted #扣' dioxy-cut (Si〇2) or nitrogen-cut (acid as shown in Figure 1E) As shown, the back side of the wafer is exposed: Next, the grinding. After that, the following is a schematic diagram of the grain structure according to an embodiment of the present invention. In the present embodiment, the grain structure produced by the above method is characterized in that a patterned first insulating layer 2G covers the sidewalls of the die 14 and the active surface, and the acidified first insulating layer 2 has a plurality of The core 21 exposes a plurality of soldering fins 15 on the active surface of the die 14, please refer to FIG. 2A and FIG. 2B simultaneously. In addition, a patterned second insulating layer 22 is disposed on the first patterned insulating layer 2G, and The second insulating layer 22 is provided with a Wei number pass 23 to expose the opening of the patterned first insulating layer 2G. The opening 21 and the channel 23 are guided to one of the solder pads 15. The material of the patterned second insulating layer 22 is an insulating material such as polyimide, cerium oxide or tantalum nitride. Please refer to FIG. 2A and FIG. 2B. In the embodiment, when the die 14 is disposed on the substrate 100, it is fixed on the substrate 1 by an adhesive layer (not shown). The opening 21 of the first insulating layer 20 and the patterned second insulating layer are patterned. The channel 23 of the 22 is formed to lead to one of the channels of the four pads 15. The filling material is injected into the channel active surface and the channel of the solder pad (reserved space) by the infusion molding technique and the solder joint 102 on the substrate 100 The connection between the die 14 and the substrate 1 can be achieved. FIG. 3A, FIG. 3B, FIG. 3C and FIG. 3D are schematic cross-sectional views showing the process of the multi-die package method according to an embodiment of the invention. As shown in FIG. 3A, a substrate 100 is provided and a plurality of crystal grains 14 are stacked on the substrate 100. An adhesive layer is disposed on the bottom of each of the crystal grains. The patterned first insulating layer 2 is coated with a crystal. The sidewall of the particle 4 and the active surface. The patterned first insulating layer 2 has a plurality of The port (not marked on the figure) exposes a plurality of soldering pads on the active surface of the die 14 (the unpatterned second insulating layer 22 is disposed on the first patterned insulating layer 2〇. This patterned second The insulating layer 22 has a plurality of channels (not shown) exposing the openings of the patterned first insulating layer 2, and the openings of the patterned first insulating layer 20 and the patterned second insulating layer 22 are guided. The channel 14 is soldered to the via (not shown), wherein the patterned first insulating layer 20 and the patterned second insulating layer 22 are made of polyimide, cerium oxide or tantalum nitride. Insulating material. 200921776 Following the above description, as shown in Fig. 3B and Fig. 3C, a mold such as a pellet 14 and a portion of the substrate 1 are provided. Injecting _ conductive L from the filling hole of the mold 40, the electrical structure 5 〇. The conductive material is a liquid metal or a liquid conductive material. The guide 50 includes an inscribed conductive portion 52 and an external conductive portion 54 and is electrically conductive, and the junction is formed by a potting technique. The conductive portion 52 is connected to the die & (not shown) and fills the channel, and the external conductive portion 54 is connected to the '= potential 52 and is columned along the sidewall of the die 14. It is connected to a plurality of solder joints of the substrate 1A. Thereafter, as shown in FIG. 3D, a package material 6 提供 is provided for = 100, the die 14 and the conductive structure 5 〇. Composite substrate Fig. 4A, Fig. 4B and Fig. 4C are flow diagrams showing different cross-sectional directions according to the present invention. In the present embodiment, the next day, the substrate is _ _ after the use of the infusion molding technology to make the conductive structure of the two structure % and ^ 14 solder pads (not marked on the map) with charm to fill the channel, Μ = the side of the grain M The wall is a plurality of solder joints of the column and the substrate 1GG (not shown in the figure after ii: 2) - package (four) 6G for covering the substrate (10), the die 14 and the above-mentioned The technology, the conductive material is injected into the die and the reserved space of the soldering pad and the soldering point on the substrate are connected to each other, and the j-to-die is connected in series. The reserved space is made by using the insulating material to cut the β on the wafer and actively on the positive electrode. The invention can eliminate the problem that the wiring process can be avoided when the wiring structure of the die package can be omitted. The invention can also reduce the space encountered by the t process, and fully utilize the plate utilization rate of the substrate, which can be effective. Shortening the Process Time and Reducing the Cost The embodiments described above are merely illustrative of the technical idea of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement 'when not Limiting the invention </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 1E and FIG. 1F are schematic views of an embodiment of the present invention. FIGS. 2A and 2B are schematic views showing an embodiment of the present invention. FIGS. 3A, 3B, 3C and 3D are diagrams according to the present invention. 4A, 4B, and 4C are schematic views of an embodiment of the present invention. [Main component symbol description] 100 substrate 102 solder joint 10 wafer 14 die 15 solder pad 20 patterning An insulating layer 21 opening 22 patterned second insulating layer 23 channel 30 adhesive layer 40 mold 10 200921776 50 conductive structure. 52 internal conductive portion. 54 external conductive portion 60 packaging material 11