SG11201901108PA - A method for transferring a useful layer - Google Patents

A method for transferring a useful layer

Info

Publication number
SG11201901108PA
SG11201901108PA SG11201901108PA SG11201901108PA SG11201901108PA SG 11201901108P A SG11201901108P A SG 11201901108PA SG 11201901108P A SG11201901108P A SG 11201901108PA SG 11201901108P A SG11201901108P A SG 11201901108PA SG 11201901108P A SG11201901108P A SG 11201901108PA
Authority
SG
Singapore
Prior art keywords
useful layer
substrate
transferring
wave
plane
Prior art date
Application number
SG11201901108PA
Inventor
Didier Landru
Mohamed Nadia Ben
Oleg Kononchuk
Frédéric Mazen
Damien Massy
Shay Reboh
François Rieutord
Original Assignee
Soitec Silicon On Insulator
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Commissariat Energie Atomique filed Critical Soitec Silicon On Insulator
Publication of SG11201901108PA publication Critical patent/SG11201901108PA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B81C1/00158Diaphragms, membranes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0191Transfer of a layer from a carrier wafer to a device wafer
    • B81C2201/0192Transfer of a layer from a carrier wafer to a device wafer by cleaving the carrier wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Micromachines (AREA)
  • Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Jigging Conveyors (AREA)

Abstract

A METHOD FOR TRANSFERRING A USEFUL LAYER The invention relates to a method for transferring a 5 useful layer (3) onto a support (4) comprising the steps of forming an embrittlement plane (2) by implanting light species into a first substrate (1), so as to form a useful layer (3) between such plane and one surface of the first substrate (1); of applying the support (4) onto the surface of the first 10 substrate (1) so as to form an assembly to be fractured (5); of applying a heat treatment for embrittling the assembly to be fractured (5); and initiating and propagating a fracture wave into the first substrate (1) along the embrittlement plane (3). According to the invention, the fracture wave is 15 initiated in a central area of the embrittlement plane (2) and the propagation speed of such wave is controlled so that the velocity thereof is sufficient. Thus, the interactions of the fracture wave with acoustic vibrations emitted upon the initiation and/or propagation thereof are limited to a 20 peripheral area of the useful layer (3). Figure 4
SG11201901108PA 2016-08-11 2017-08-01 A method for transferring a useful layer SG11201901108PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1657722A FR3055063B1 (en) 2016-08-11 2016-08-11 METHOD OF TRANSFERRING A USEFUL LAYER
PCT/FR2017/052161 WO2018029419A1 (en) 2016-08-11 2017-08-01 Method for transferring a useful layer

Publications (1)

Publication Number Publication Date
SG11201901108PA true SG11201901108PA (en) 2019-03-28

Family

ID=57121393

Family Applications (2)

Application Number Title Priority Date Filing Date
SG11201901108PA SG11201901108PA (en) 2016-08-11 2017-08-01 A method for transferring a useful layer
SG10201912610SA SG10201912610SA (en) 2016-08-11 2017-08-01 A method for transferring a useful layer

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG10201912610SA SG10201912610SA (en) 2016-08-11 2017-08-01 A method for transferring a useful layer

Country Status (9)

Country Link
US (2) US10950491B2 (en)
EP (1) EP3497713B1 (en)
JP (1) JP6977023B2 (en)
KR (1) KR102489395B1 (en)
CN (1) CN109564891B (en)
FR (1) FR3055063B1 (en)
SG (2) SG11201901108PA (en)
TW (1) TWI738834B (en)
WO (1) WO2018029419A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3091032B1 (en) * 2018-12-20 2020-12-11 Soitec Silicon On Insulator Method of transferring a surface layer to cavities
FR3091620B1 (en) 2019-01-07 2021-01-29 Commissariat Energie Atomique Layer transfer method with localized reduction of an ability to initiate a fracture

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Also Published As

Publication number Publication date
JP2019531594A (en) 2019-10-31
US11670540B2 (en) 2023-06-06
FR3055063B1 (en) 2018-08-31
FR3055063A1 (en) 2018-02-16
CN109564891A (en) 2019-04-02
JP6977023B2 (en) 2021-12-08
KR20190037324A (en) 2019-04-05
EP3497713B1 (en) 2020-04-08
US20210202302A1 (en) 2021-07-01
US10950491B2 (en) 2021-03-16
KR102489395B1 (en) 2023-01-18
EP3497713A1 (en) 2019-06-19
TW201820428A (en) 2018-06-01
CN109564891B (en) 2023-08-29
SG10201912610SA (en) 2020-02-27
TWI738834B (en) 2021-09-11
WO2018029419A1 (en) 2018-02-15
US20190221471A1 (en) 2019-07-18

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