SG11201808636TA - Tsv structure planarization process and apparatus - Google Patents

Tsv structure planarization process and apparatus

Info

Publication number
SG11201808636TA
SG11201808636TA SG11201808636TA SG11201808636TA SG11201808636TA SG 11201808636T A SG11201808636T A SG 11201808636TA SG 11201808636T A SG11201808636T A SG 11201808636TA SG 11201808636T A SG11201808636T A SG 11201808636TA SG 11201808636T A SG11201808636T A SG 11201808636TA
Authority
SG
Singapore
Prior art keywords
shanghai
bld
road
international
metal layer
Prior art date
Application number
SG11201808636TA
Inventor
Yinuo Jin
Yingwei Dai
Guipu Yang
Jian Wang
Hui Wang
Original Assignee
Acm Res Shanghai Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acm Res Shanghai Inc filed Critical Acm Res Shanghai Inc
Publication of SG11201808636TA publication Critical patent/SG11201808636TA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -, Organization MD 1101111 0 11101 0I0 11111 MEM 0 111 010 11111 001 1011 0111 00 111110 HOED International Bureau .. .... ..Yejd ..... .....:;. (10) International Publication Number (43) International Publication Date WO 2017/173613 Al 12 October 2017(12.10.2017) WIPO I PCT (51) (21) (22) (25) Filing Language: (26) Publication Language: (71) (72) International Patent Classification: (74) Agent: SHANGHAI PATENT & TRADEMARK LAW HO1L 21/768 (2006.01) OFFICE, LLC; 435 Guiping Road, Shanghai 200233 (CN). International Application Number: PCT/CN2016/078656 (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, International Filing Date: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, 7 April 2016 (07.04.2016) BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, English DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, English KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, Applicant: ACM RESEARCH (SHANGHAI) INC. MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, [CN/CN]; Bld. 4, No. 1690 Cailun Road, Zhangjiang PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, High-Tech Park, Shanghai 201203 (CN). SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. Inventors: MN, Yinuo; Bld. 4, No. 1690 Cailun Road, Zhangjiang High-Tech Park, Shanghai 201203 (CN). DAI, (84) Designated States (unless otherwise indicated, for every Yingwei; Bld. 4, No. 1690 Cailun Road, Zhangjiang High- kind of regional protection available): ARIPO (BW, GH, Tech Park, Shanghai 201203 (CN). YANG, Guipu; Bld. 4, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, No. 1690 Cailun Road, Zhangjiang High-Tech Park, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, Shanghai 201203 (CN). WANG, Man; Bld. 4, No. 1690 TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, Cailun Road, Zhangjiang High-Tech Park, Shanghai DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, 201203 (CN). WANG, Hui; Bld. 4, No. 1690 Cailun LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, Road, Zhangjiang High-Tech Park, Shanghai 201203 SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, (CN) GW, KM, ML, MR, NE, SN, TD, TG). . Published: — with international search report (Art. 21(3)) _ TSV STRUCTURE PLANARIZATION PROCESS AND APPARATUS : A TSV structure in the substrate (101), an oxide layer (103) formed on the substrate (101), a barrier bottom and sidewall of the vias (102), a metal layer (105) formed in the vias (102) planarization process comprises: process (301); and removing metal layer residual and the barrier layer on the non (305). --- 301 303 305 includes a substrate (101), vias (102) layer (104) formed on the oxide layer and on the barrier layer (104).The TSV area of the substrate by a stress-free -recessed area by a chemical wet etch pro - (54) Title: = = = removing all metal layer deposited on a non- recessed area by a stress-free polishing process = = = = V = removing metal layer residual on the non- recessed area by a metal layer chemical wet etch process = = — = V removing barrier layer on the non-recessed area by a barrier layer chemical wet etch process 1-1 en 11 IN en ,-1 (57) ::::; formed N (103), 0 structure polishing .,. cess (303) Fig 3 planarization process and apparatus. The TSV structure removing all metal layer formed on a non-recessed
SG11201808636TA 2016-04-07 2016-04-07 Tsv structure planarization process and apparatus SG11201808636TA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/078656 WO2017173613A1 (en) 2016-04-07 2016-04-07 Tsv structure planarization process and apparatus

Publications (1)

Publication Number Publication Date
SG11201808636TA true SG11201808636TA (en) 2018-10-30

Family

ID=60000123

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201808636TA SG11201808636TA (en) 2016-04-07 2016-04-07 Tsv structure planarization process and apparatus

Country Status (5)

Country Link
KR (1) KR102599825B1 (en)
CN (1) CN108886016B (en)
SG (1) SG11201808636TA (en)
TW (1) TWI774645B (en)
WO (1) WO2017173613A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113059405A (en) * 2019-12-30 2021-07-02 盛美半导体设备(上海)股份有限公司 Processing method and cleaning device for semiconductor structure

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020192941A1 (en) * 2001-06-19 2002-12-19 Chia-Lin Hsu Method for reducing dishing in copper chemical mechanical polishing process
US8372757B2 (en) * 2003-10-20 2013-02-12 Novellus Systems, Inc. Wet etching methods for copper removal and planarization in semiconductor processing
JP5412517B2 (en) * 2008-08-20 2014-02-12 エーシーエム リサーチ （シャンハイ） インコーポレーテッド Barrier layer removal method and apparatus
US8415254B2 (en) * 2008-11-20 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for removing dummy poly in a gate last process
CN101882595B (en) * 2009-05-08 2014-07-09 盛美半导体设备（上海）有限公司 Method and device for removing barrier layer
US9305865B2 (en) * 2013-10-31 2016-04-05 Micron Technology, Inc. Devices, systems and methods for manufacturing through-substrate vias and front-side structures
US8956974B2 (en) * 2012-06-29 2015-02-17 Micron Technology, Inc. Devices, systems, and methods related to planarizing semiconductor devices after forming openings
CN105144363B (en) * 2012-11-27 2018-05-18 盛美半导体设备（上海）有限公司 The forming method of interconnection structure
WO2014172835A1 (en) * 2013-04-22 2014-10-30 Acm Research (Shanghai) Inc Method and apparatus for through-silicon vias reveal
CN103474394B (en) * 2013-09-11 2015-07-08 华进半导体封装先导技术研发中心有限公司 TSV process method without metal CMP
CN103474395B (en) * 2013-09-13 2016-08-24 华进半导体封装先导技术研发中心有限公司 A kind of TSV planarization method
CN105336672A (en) * 2014-07-24 2016-02-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and formation method therefor
CN105390384B (en) * 2015-10-29 2018-05-01 上海集成电路研发中心有限公司 A kind of method that silica is removed during unstressed electrochemical polish copper

Also Published As

Publication number Publication date
TW201737417A (en) 2017-10-16
CN108886016A (en) 2018-11-23
CN108886016B (en) 2023-03-10
KR102599825B1 (en) 2023-11-08
WO2017173613A1 (en) 2017-10-12
TWI774645B (en) 2022-08-21
KR20180133433A (en) 2018-12-14

Similar Documents

Publication Publication Date Title
SG11201804041QA (en) High conductivity graphane-metal composite and methods of manufacture
SG11201901548SA (en) Anti-tim-3 antibodies and use thereof
SG11201806624XA (en) Deposition of molybdenum thin films using a molybdenum carbonyl precursor
SG11201807741SA (en) Conductive structures, systems and devices including conductive structures and related methods
SG11201901210UA (en) Ferroelectric memory cells
SG11201807561YA (en) System and method for automatic posture calibration
SG11201903487SA (en) PROCESS FOR THE PREPARATION OF PYRAZOLO[1,5-a]PYRIMIDINES AND SALTS THEREOF
SG11201808125RA (en) Methods for solid tumor treatment
SG11201810522UA (en) Anti-cd40 antibodies and their uses
SG11201900723YA (en) Apparatus and system for enhanced selective contaminant removal processes related thereto
SG11201908075UA (en) A microneedle device
SG11201408451WA (en) Use of vacuum chucks to hold a wafer or wafer sub-stack
SG11201407650VA (en) Composition and process for stripping photoresist from a surface including titanium nitride
SG11201811149TA (en) METABOLIC DRUG LOADING OF EVs
SG11201909009TA (en) Catheter securement device with window
SG11201804185VA (en) Features on a porous membrane
SG11201901463YA (en) Apparatus and methods for atomic layer deposition
SG11201809356YA (en) Multilayer coating and process of preparing the multilayer coating
SG11201901873PA (en) Tablet compositions
SG11201811778PA (en) Substrate supporting apparatus
SG11201807697QA (en) Intra-mould substrate
SG11201809413RA (en) Detection of chromosome interaction relevant to breast cancer
SG11201804654WA (en) Apparatus for holding substrate
SG11201804440XA (en) Chemical reprogramming of human glial cells into neurons with small molecule cocktail
SG11201806880QA (en) Communicating with two or more slaves