SG11201807926PA - A through silicon interposer wafer and method of manufacturing the same - Google Patents

A through silicon interposer wafer and method of manufacturing the same

Info

Publication number
SG11201807926PA
SG11201807926PA SG11201807926PA SG11201807926PA SG11201807926PA SG 11201807926P A SG11201807926P A SG 11201807926PA SG 11201807926P A SG11201807926P A SG 11201807926PA SG 11201807926P A SG11201807926P A SG 11201807926PA SG 11201807926P A SG11201807926P A SG 11201807926PA
Authority
SG
Singapore
Prior art keywords
international
interposer wafer
singapore
manufacturing
silicon interposer
Prior art date
Application number
SG11201807926PA
Inventor
Navab Singh
Daw Don Cheam
Original Assignee
Agency Science Tech & Res
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency Science Tech & Res filed Critical Agency Science Tech & Res
Publication of SG11201807926PA publication Critical patent/SG11201807926PA/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00563—Avoid or control over-etching
    • B81C1/00587—Processes for avoiding or controlling over-etching not provided for in B81C1/00571 - B81C1/00579
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0315—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0323—Grooves
    • B81B2203/033—Trenches
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/094—Feed-through, via
    • B81B2207/095—Feed-through, via through the lid
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0132—Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0135—Controlling etch progression
    • B81C2201/014—Controlling etch progression by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)
  • Extrusion Moulding Of Plastics Or The Like (AREA)
  • Pressure Sensors (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -, Organization 111111111111101101010111110101111101101110011111H011111111111111110111111 International Bureau ... .... ..Yjd ..... ...,/ (10) International Publication Number (43) International Publication Date WO 2017/164816 Al 28 September 2017 (28.09.2017) WIP0 I PCT (51) International Patent Classification: (81) Designated States (unless otherwise indicated, for every HO1L 23/48 (2006.01) B81B 7/00 (2006.01) kind of national protection available): AE, AG, AL, AM, HO1L 23/52 (2006.01) AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, (21) International Application Number: DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, PCT/SG2017/050145 HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, (22) International Filing Date: KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, 23 March 2017 (23.03.2017) MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, (25) Filing Language: English RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, (26) Publication Language: English TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (30) Priority Data: 10201602341R 24 March 2016 (24.03.2016) SG (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, (71) Applicant: AGENCY FOR SCIENCE, TECHNOLOGY GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, AND RESEARCH [SG/SG]; 1 Fusionopolis Way, #20-10 TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, Connexis North Tower, Singapore 138632 (SG). TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, (72) Inventors: SINGH, Navab; c/o Industry Development, In- stitute of Microelectronics, 2 Fusionopolis Way, #08-02 LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, Innovis Tower, Singapore 138634 (SG). CHEAM, Daw SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Don; c/o Industry Development, Institute of Microelectron- ics, 2 Fusionopolis Way, #08-02 Innovis Tower, Singapore Declarations under Rule 4.17: 138634 (SG). — of inventorship (Rule 4.17(iv)) (74) Agent: SPRUSON & FERGUSON (ASIA) PTE LTD; Published: P.O. Box 1531, Robinson Road Post Office, Singapore 903031 (SG). — with international search report (Art. 21(3)) (54) Title: A THROUGH SILICON INTERPOSER WAFER AND METHOD OF MANUFACTURING 23 22 23 60 k 22 I 50 31 53 is 23 32 80 22 22„, THE SAME 11 1-1 12 51 24 GO 7 — 1 I / f iv (”) 21 FIG. 1A 22 23 24 11 1-1 10 IN 1-1 (57) : A Through Silicon Interposer Wafer and Method of Manufacturing the Same A through silicon interposer wafer hay- = ing at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide 0 support for walls of the at least one cavity during subsequent processing of the interposer wafer.
SG11201807926PA 2016-03-24 2017-03-23 A through silicon interposer wafer and method of manufacturing the same SG11201807926PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10201602341R 2016-03-24
PCT/SG2017/050145 WO2017164816A1 (en) 2016-03-24 2017-03-23 A through silicon interposer wafer and method of manufacturing the same

Publications (1)

Publication Number Publication Date
SG11201807926PA true SG11201807926PA (en) 2018-10-30

Family

ID=59900635

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201807926PA SG11201807926PA (en) 2016-03-24 2017-03-23 A through silicon interposer wafer and method of manufacturing the same

Country Status (3)

Country Link
US (1) US10882737B2 (en)
SG (1) SG11201807926PA (en)
WO (1) WO2017164816A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018113218B3 (en) 2018-06-04 2019-09-05 RF360 Europe GmbH Wafer level package and manufacturing process
US11174157B2 (en) * 2018-06-27 2021-11-16 Advanced Semiconductor Engineering Inc. Semiconductor device packages and methods of manufacturing the same
US11220423B2 (en) * 2018-11-01 2022-01-11 Invensense, Inc. Reduced MEMS cavity gap

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3751625B2 (en) * 2004-06-29 2006-03-01 新光電気工業株式会社 Manufacturing method of through electrode
CN102412228B (en) 2011-10-31 2014-04-02 中国科学院微电子研究所 Coaxial through-silicon-via interconnection structure and manufacturing method thereof
US9466532B2 (en) * 2012-01-31 2016-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Micro-electro mechanical system (MEMS) structures with through substrate vias and methods of forming the same
US10160638B2 (en) 2013-01-04 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor structure
US9764946B2 (en) 2013-10-24 2017-09-19 Analog Devices, Inc. MEMs device with outgassing shield
TWI550737B (en) 2014-08-11 2016-09-21 精材科技股份有限公司 Chip package and method thereof
WO2016204693A1 (en) * 2015-06-17 2016-12-22 Agency For Science, Technology And Research Semiconductor packages and methods for fabricating semiconductor packages
CN105174195A (en) 2015-10-12 2015-12-23 美新半导体（无锡）有限公司 WLP (wafer-level packaging) structure and method for cavity MEMS (micro-electromechanical system) device

Also Published As

Publication number Publication date
WO2017164816A8 (en) 2018-04-26
WO2017164816A1 (en) 2017-09-28
US10882737B2 (en) 2021-01-05
US20190084826A1 (en) 2019-03-21

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