SG11201806627SA - Curable resin composition and fan-out wafer level package - Google Patents

Curable resin composition and fan-out wafer level package

Info

Publication number
SG11201806627SA
SG11201806627SA SG11201806627SA SG11201806627SA SG11201806627SA SG 11201806627S A SG11201806627S A SG 11201806627SA SG 11201806627S A SG11201806627S A SG 11201806627SA SG 11201806627S A SG11201806627S A SG 11201806627SA SG 11201806627S A SG11201806627S A SG 11201806627SA
Authority
SG
Singapore
Prior art keywords
resin composition
curable resin
fan
wafer level
level package
Prior art date
Application number
SG11201806627SA
Inventor
Chihiro Funakoshi
Kazuya Sato
Nobuhito Ito
Original Assignee
Taiyo Ink Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Ink Mfg Co Ltd filed Critical Taiyo Ink Mfg Co Ltd
Publication of SG11201806627SA publication Critical patent/SG11201806627SA/en

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L101/00—Compositions of unspecified macromolecular compounds
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08J—WORKING-UP; GENERAL PROCESSES OF COMPOUNDING; AFTER-TREATMENT NOT COVERED BY SUBCLASSES C08B, C08C, C08F, C08G or C08H
    • C08J3/00—Processes of treating or compounding macromolecular substances
    • C08J3/24—Crosslinking, e.g. vulcanising, of macromolecules
    • C08J3/243—Two or more independent types of crosslinking for one or more polymers
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L63/00—Compositions of epoxy resins; Compositions of derivatives of epoxy resins
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08J—WORKING-UP; GENERAL PROCESSES OF COMPOUNDING; AFTER-TREATMENT NOT COVERED BY SUBCLASSES C08B, C08C, C08F, C08G or C08H
    • C08J3/00—Processes of treating or compounding macromolecular substances
    • C08J3/24—Crosslinking, e.g. vulcanising, of macromolecules
    • C08J3/244—Stepwise homogeneous crosslinking of one polymer with one crosslinking system, e.g. partial curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Polymers & Plastics (AREA)
  • Medicinal Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Compositions Of Macromolecular Compounds (AREA)
  • Epoxy Resins (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Macromonomer-Based Addition Polymer (AREA)

Abstract

Provided are a curable resin composition that can reduce the amount of warpage both at a temperature for mounting a 5 semiconductor wafer or a semiconductor package, in particular, a fan-out wafer level package (FO-WLP) and at room temperature for, for example, conveying wafers, and a fan-out wafer level package that includes a warpage correction layer made of a cured product of the curable resin composition. The 10 curable resin composition is curable through at least two types of curing reactions, and includes a curable component (A1) that contracts in volume through one curing reaction, and a curable component (B1) that contracts in volume through another curing reaction.
SG11201806627SA 2016-02-17 2017-02-09 Curable resin composition and fan-out wafer level package SG11201806627SA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016028046A JP5989929B1 (en) 2016-02-17 2016-02-17 Curable resin composition
PCT/JP2017/004777 WO2017141818A1 (en) 2016-02-17 2017-02-09 Curable resin composition and fan out type wafer level package

Publications (1)

Publication Number Publication Date
SG11201806627SA true SG11201806627SA (en) 2018-09-27

Family

ID=56871754

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201806627SA SG11201806627SA (en) 2016-02-17 2017-02-09 Curable resin composition and fan-out wafer level package

Country Status (8)

Country Link
EP (1) EP3419051A4 (en)
JP (1) JP5989929B1 (en)
KR (1) KR102103660B1 (en)
CN (1) CN108701657B (en)
MY (1) MY189981A (en)
SG (1) SG11201806627SA (en)
TW (1) TWI724105B (en)
WO (1) WO2017141818A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6224188B1 (en) * 2016-08-08 2017-11-01 太陽インキ製造株式会社 Semiconductor encapsulant
WO2018181686A1 (en) * 2017-03-29 2018-10-04 太陽インキ製造株式会社 Warpage correction material and method for manufacturing fan out-type wafer level package
JP6423119B2 (en) * 2017-03-29 2018-11-14 太陽インキ製造株式会社 Warpage correction material and manufacturing method of fan-out type wafer level package
JP6998250B2 (en) * 2018-03-27 2022-01-18 日本カーバイド工業株式会社 Infrared laser irradiation resin composition and infrared laser irradiation resin film
JP7137395B2 (en) * 2018-08-07 2022-09-14 東京応化工業株式会社 LAMINATED PRODUCTION METHOD, LAMINATED BODY, AND ELECTRONIC DEVICE MANUFACTURING METHOD
US11421316B2 (en) * 2018-10-26 2022-08-23 Applied Materials, Inc. Methods and apparatus for controlling warpage in wafer level packaging processes

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1250663C (en) * 2001-06-25 2006-04-12 泰勒弗氏股份有限公司 Anisotropic conductive adhesives having enhanced viscosity and bondng methods and integrated circuit packages using same
TWI297722B (en) * 2002-03-29 2008-06-11 Telephus Inc Anisotropic conductive adhesives having enhanced viscosity and bonding methods and integrated circuit packages
JP2004099635A (en) * 2002-09-04 2004-04-02 Taiyo Ink Mfg Ltd Photocurable, thermosetting resin composition, its molded product and cured product thereof
JP2004253643A (en) * 2003-02-20 2004-09-09 Lintec Corp Method for manufacturing semiconductor chip
JP2009223014A (en) * 2008-03-17 2009-10-01 Hanna System:Kk Focus adjustment device
US20100167471A1 (en) * 2008-12-30 2010-07-01 Stmicroelectronics Asia Pacific Pte. Ltd. Reducing warpage for fan-out wafer level packaging
US9054111B2 (en) * 2009-04-07 2015-06-09 Freescale Semiconductor, Inc. Electronic device and method of packaging an electronic device
JP2010263119A (en) * 2009-05-08 2010-11-18 Panasonic Corp Nonvolatile semiconductor memory device and method of manufacturing the same
JP2011075787A (en) * 2009-09-30 2011-04-14 Sekisui Chem Co Ltd Photosensitive composition
JP2012178422A (en) 2011-02-25 2012-09-13 Fujikura Ltd Semiconductor device manufacturing method, semiconductor device manufacturing apparatus and substrate holding jig
JP6019550B2 (en) 2011-08-09 2016-11-02 富士通株式会社 Manufacturing method of electronic device
JP2013168615A (en) * 2012-02-17 2013-08-29 Toppan Printing Co Ltd Semiconductor package substrate and manufacturing method therefor

Also Published As

Publication number Publication date
JP5989929B1 (en) 2016-09-07
KR20180104306A (en) 2018-09-20
CN108701657A (en) 2018-10-23
WO2017141818A1 (en) 2017-08-24
EP3419051A1 (en) 2018-12-26
EP3419051A4 (en) 2019-05-29
MY189981A (en) 2022-03-22
TW201800493A (en) 2018-01-01
KR102103660B1 (en) 2020-04-22
CN108701657B (en) 2022-05-13
TWI724105B (en) 2021-04-11
JP2017147331A (en) 2017-08-24

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